A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 6, 2002, Pages 735-750

  Shibata, Nobutaro ^a,b   Watanabe, Mayumi ^a   Tanabe, Yasuyuki ^a  

^a NTT CORPORATION   (Japan)

^b Sapporo Medical Center   (Japan)

Author keywords

CMOS; Counter; Current sense; Data driven; Double rail XOR; Dual port; FIFO; Gray code; High speed; Low power; Memory; Size configurable; SRAM

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; LSI CIRCUITS; RANDOM ACCESS STORAGE; SHIFT REGISTERS;

DATA DRIVEN; DOUBLE-RAIL XOR; DUAL PORT; FIRST-IN FIRST-OUT DATA STORAGE; GRAY CODE; SIZE-CONFIGURABLE;

SEMICONDUCTOR STORAGE;

EID: 0036612248     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.1004578     Document Type: Article

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