Double-edge-triggered address pointer for low-power high-speed FIFO memories

Electronics Letters

Volumn 33, Issue 5, 1997, Pages 387-389

  Wang, H ^a   Liu, P C ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Integrated memory circuits; VLSI

Indexed keywords

CAPACITANCE; CELLULAR ARRAYS; ENERGY UTILIZATION; FLIP FLOP CIRCUITS; SHIFT REGISTERS; VLSI CIRCUITS;

ADDRESS POINTER DESIGN; INTEGRATED MEMORY CIRCUITS; POWER CONSUMPTION; SHIFT LOCK FREQUENCY; SHIFTING CLOCKLINES;

INTEGRATED OPTOELECTRONICS;

EID: 0031071782     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19970244     Document Type: Article

References (4)

1. MUKHERJEE, A.: 'nMOS and CMOS VLSI systems design' (PrenticeHall Inc., New Jersey, USA, 1986). p.110
2. SHOJI, M.: 'CMOS digital circuit technology' (Prentice-Hall Inc., New Jersey, USA, 1987). p. 83
3. HASHIMOTO, M., and NOMURA, M.: 'A 20-ns 256K×4 FIFO memory', IEEE J. Solid-State Circuits. 1988, 23, (2), pp. 490-499
4. HOSSAIN, R., WRONSKI, L., and ALBICKI, A.: 'Low power design using double edge triggered flip-flop'. IEEE Trans. VLSI Syst., 1994, 2, (2). pp. 261-265