Implementation of sub-10 ns serial access mode to a standard 64-mb DRAM

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1991, Pages

  Watanabe, Yohji ^a   Tsuchida, Kenji ^a   Oowaki, Yukihito ^a   Takashima, Daisaburo ^a   Ohta, Masako ^a   Nakano, Hiroaki ^a   Watanabe, Shigeyoshi ^a   Ohuchi, Kazunori ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

IMAGE PROCESSING - COMPONENTS; INTEGRATED CIRCUITS, CMOS - DESIGN;

DRAMS; IMAGE PROCESSING CHIP; MEMORY CHIPS; SPECIALTY RAMS;

DATA STORAGE, DIGITAL;

EID: 0026367499     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)