A 9.6 Gb/s HEMT ATM switch LSI for B-ISDN

GaAs IC Symposium Technical Digest 1992

Volumn , Issue , 1992, Pages 295-298

  Watanabe, Y ^a   Nakasha, Y ^a   Kato, Y ^a   Odani, K ^a   Abe, M ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; GALLIUM ARSENIDE; III-V SEMICONDUCTORS; INTELLIGENT AGENTS; INTERNET PROTOCOLS; LSI CIRCUITS; SEMICONDUCTING GALLIUM;

BROADBAND INTEGRATED SERVICES DIGITAL NETWORKS; CONTROL LOGIC; DIRECT COUPLED; FIRST IN FIRST OUTS; HEMT TECHNOLOGIES; HIGH-SPEED PERFORMANCE; OPERATION FREQUENCY; STATIC MEMORY;

ASYNCHRONOUS TRANSFER MODE;

EID: 85027100117     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/GAAS.1992.247277     Document Type: Conference Paper

References (8)

1. Y. Kato, et al., "A development of a high speed ATM switching LSIC," ICC '90, 310.3, 1990
2. L. Cloetens, et al., "A 600Mb/s 16×16 switching element chipset for broadband ISDN," in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 240-241
3. S. Tanaka, et al., "A 400Mb/s 8×8 BiCMOS ATM switch LSI with 128kb on-chip shared memory," in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 242-243
4. M. Akata, et al., "A scheduling content-addressable memory for ATM space-division switch control," in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 244-245
5. Y. Watanabe et al., "A half-micron HEMT LSI for a multi-bit data register," in ISSCC Dig. Tech. Papers, Feb. 1988, pp. 86-87
6. Y. Asada et al., "A gigahertz cryogenic HEMT pseudorandom number generator chip set," in ISSCC Dig. Tech. Papers, Feb. 1990, pp. 186-187.
7. M. Suzuki, et al., "1.2-ns HEMT 64-kb SRAM," IEEE J. Solid-State Circuits. Vol. SC-26 pp. 1571-1576 Nov. 1991
8. S. Notomi, et al., "A 45K-gate HEMT array with 35-ps DCFL and 50-ps BDCFL gates," IEEE J. Solid-State Circuits. Vol. SC-26 pp. 1621-1625 Nov. 1991