A 3V, 100MHz, 35mW, dynamic line memory macro cell for HDTV applications

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1992, Pages

  Kimura, M ^a   Masuda, S ^a   Ohki, M ^a   Yamashita, Y ^a   Okada, K ^a   Horiba, Y ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT ARCHITECTURES; CMOS LOGIC PROCESS; EMBEDDED TESTS; HIGH-SPEED OPERATION; LOW POWER SUPPLY; MACRO CELLS; MEMORY MACRO; MEMORY STRUCTURE; POWER SUPPLY;

HIGH DEFINITION TELEVISION; INTEGRATED CIRCUITS; LOW POWER ELECTRONICS;

MACROS;

EID: 33747802132     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.1992.591151     Document Type: Conference Paper

References (5)

1. SMPTE 240M, "Signal Parameters 1125/60 High-Definition Production System", SMPTE J., p.1150-, Nov. 1987.
2. BERND ZEHNER et al., "A CMOS VLSI Chip for Filtering of TV Pictures in Two Dimensions.", IEEE J. Solid-State Circuits, vol. SC-21, no.5, p.797, Oct. 1986.
3. Matsumura T. et al. "A High - Performance Reconfigurable Line Memory Macrocell for Video Signal Processing ASICs.", IEICE Trans. Japan, E74, 11, pp.3787-3795, Nov. 1991.
4. Masuda S.et al., "A study of Line Memory for HDTV Applications", 1992 Spring Natl.Conv. Rec., IEICE, will be published on Apr.1992.
5. Ninomiya Y. et al., "An HDTV Broadcasting System Utilizing a Bandwidth Compression Technique - MUSE.", IEEE Trans. on Broadcasting, vol. BC-33, no.4, p.130, Dec.1987.