A scalable pipelined architecture for fast buffer SRAM's

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 3, 1996, Pages 419-429

  Nicol, C J ^a,b,c   Dickinson, A G ^a,c,d,e  

^a LUCENT TECHNOLOGIES   (United States)

^b UNIVERSITY OF NEW SOUTH WALES   (Australia)

^c VLSI Systems Research Department

^d UNIVERSITY OF ADELAIDE   (Australia)

^e Columbia University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DECODING; PACKET SWITCHING; PIPELINE PROCESSING SYSTEMS; REDUNDANCY; SIGNAL PROCESSING;

ACCESS FREQUENCY; DATA BUFFERING; DATA DISTRIBUTION; MEMORY BLOCKS;

RANDOM ACCESS STORAGE;

EID: 0030110604     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.494204     Document Type: Article

References (14)

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