A capacitorless double-gate DRAM cell

IEEE Electron Device Letters

Volumn 23, Issue 6, 2002, Pages 345-347

  Kuo, Charles ^b   King, Tsu Jae ^a,b   Hu, Chenming ^a,b  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Double gate MOSFETs; DRAM; Fully depleted; Scaled CMOS; Silicon on insulator (SOI) MOSFETs

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); IMPACT IONIZATION; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

DOPANT FLUCTUATIONS; DRAIN CURRENT;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0036610025     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2002.1004230     Document Type: Letter

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