Limitations and challenges of multigigabit DRAM chip design

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 5, 1997, Pages 624-634

  Itoh, Kiyoo ^a,b,c,d   Nakagome, Yoshinobu ^a,b,c,e,f   Kimura, Shin'ichiro ^a,b,c,d,g   Watanabe, Takao ^a,b,f,h,i  

^a IEEE   (United States)

^b HITACHI LTD   (Japan)

^c Tohoku University ^*

^d TOHOKU UNIVERSITY   (Japan)

^e TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^f Institute of Electronics   (Japan)

^g UNIVERSITY OF TOKYO   (Japan)

^h KEIO UNIVERSITY   (Japan)

ⁱ YALE UNIVERSITY   (United States)

Author keywords

DRAM chip; Embedded DRAM; I O; Low voltage circuits; Memory array; Memory cell; Packaging

Indexed keywords

CELLULAR ARRAYS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT; ION IMPLANTATION; MOSFET DEVICES; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; SEMICONDUCTOR JUNCTIONS;

DYNAMIC RANDOM ACCESS MEMORY (DRAM) CHIPS;

RANDOM ACCESS STORAGE;

EID: 0031139365     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.568820     Document Type: Article

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