Incremental diagnosis of multiple open-interconnects

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 1085-1092

  Liu, J Brandon ^a   Veneris, Andreas ^a   Takahashi, Hiroshi ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b EHIME UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT SIMULATION; INCREMENTAL DIAGNOSIS; MULTIPLE OPEN INTERCONNECTS;

ALGORITHMS; COMBINATORIAL CIRCUITS; FAILURE ANALYSIS; HEURISTIC METHODS; INTERCONNECTION NETWORKS; PHASE SPACE METHODS; SEQUENTIAL CIRCUITS;

INTEGRATED CIRCUIT TESTING;

EID: 0036446344     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2002.1041865     Document Type: Conference Paper

References (20)

1. M. Abramovici, M. A. Breuer, and A. D. Friedman. Digital Systems Testing and Testable Design. IEEE Press, Piscataway, New Jersey, 1994.
2. V. Boppana and M. Fujita. Modeling the unknown! towards model-independent fault and error diagnosis. Proc. ITC, pages 1094-1101, 1998.
3. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits, Kluwer Academic Publishers, 2000.
4. V. Champac, A. Rubio, and J. Figueras. Electrical model of the floating gate defect in cmos ics: Implication on iddq testing. IEEE Trans. CAD, pages 359-369, 1994.
5. C. Di and J. A. G. Jess, On accurate modeling and efficient simulation of cmos opens. Proc. IEEE ITC, pages 875-882, 1993.
6. I. Hamzaoglu and J. H. Patel. New techniques for deterministic test pattern generation. Proc. IEEE VTS, pages 138-148, 1998.
7. S. Y. Huang and K. T. Cheng. Errortracer: Design error diagnosis based on fault simulation techniques. IEEE Trans. CAD, 18(9):1341-1352, September 1999.
8. H. Konuk. Fault simulation of interconnect opens in digital cmos circuits. Proc. IEEE ICCAD, pages 548-554, 1997.
9. H. Konuk and F. J. Ferguson. Oscillation and sequential behavior caused by opens in the routing of digital cmos circuits. IEEE Trans. CAD, 18:1200-1210, 1998.
10. D. B. Lavo, T. Larrabee, and B. Chess. Beyond the byzantine generals: Unexpected behavior and bridging fault diagnosis. Proc. IEEE ITC, pages 611-619, 1996.
11. J. B. Liu, A. Veneris, and M. S. Abadir. Efficient and exact diagnosis of multiple stuck-at faults. Proc. IEEE LATW, 2002.
12. S. M. Reddy, H. Tang, I. Pomeranz, S. Kajihara, and K. Kinoshita. On testing of interconnect open defects in combinational logic circuits with stems of large fanout. Proc. European Test Workshop, pages 127-128, 2002.
13. E. Sentovich, K. Singh, C. Moon, H. Savoj, R. Brayton, and A. Sangiovanni-Vincentelli. Sequential circuit design using synthesis and optimization. Proc. Int'l Conference on Computer Design, pages 328-333, 1992.
14. N. Sridhar and M. S. Hsiao. On efficient error diagnosis of digital circuits. Proc. IEEE ITC, pages 678-687, 2001.
15. A. Veneris and I. N. Hajj. Design error diagnosis and correction via test vector simulation. IEEE Trans. CAD, 18(12):1803-1816, December 1999.
16. A. Veneris, J. B. Liu, M. Amiri, and M. S. Abadir. Incremental diagnosis and debugging of multiple faults and errors. Proc. IEEE DATE, pages 716-721, 2002.
17. S. Venkataraman and S. B. Drummonds. A technique for logic fault diagnosis of interconnect open defects. Proc. IEEE VTS, pages 313-318, 2000.
18. S. Venkataraman and S. B. Drummonds. Poirot: Applications of a logic fault diagnosis tool. IEEE Design and Test of Computers, pages 19-20, Jan.-Feb. 2001.
19. S. Venkataraman and W. K. Fuchs. A deductive technique for diagnosis of bridging faults. Proc. IEEE ICCAD, pages 562-567, 1997.
20. J. Wu and E. M. Rudnick. Bridge fault diagnosis using stuck-at fault simulation. IEEE Trans. CAD, 19(4):489-495, 2000.