-
3
-
-
0032319387
-
New techniques for deterministic test pattern generation
-
I. Hamzaoglu and J. H. Patel. New techniques for deterministic test pattern generation. Proc. IEEE VTS, pages 138-148, 1998.
-
(1998)
Proc. IEEE VTS
, pp. 138-148
-
-
Hamzaoglu, I.1
Patel, J.H.2
-
4
-
-
0142174913
-
Towards the logic defect diagnosis for partialscan designs
-
S. Y. Huang. Towards the logic defect diagnosis for partialscan designs. Proc. IEEE ASP-DAC, pages 313-318, 2001.
-
(2001)
Proc. IEEE ASP-DAC
, pp. 313-318
-
-
Huang, S.Y.1
-
5
-
-
0032595832
-
Errortracer: Design error diagnosis based on fault simulation techniques
-
September
-
S. Y. Huang and K. T. Cheng. Errortracer: Design error diagnosis based on fault simulation techniques. IEEE Trans. CAD, 18(9):1341-1352, September 1999.
-
(1999)
IEEE Trans. CAD
, vol.18
, Issue.9
, pp. 1341-1352
-
-
Huang, S.Y.1
Cheng, K.T.2
-
6
-
-
0032638330
-
Simulation-based error diagnosis and correction in combinational digital circuits
-
D. Nayak and D. M. H.Walker. Simulation-based error diagnosis and correction in combinational digital circuits. Proc. IEEE VTS, pages 70-78, 1999.
-
(1999)
Proc. IEEE VTS
, pp. 70-78
-
-
Nayak, D.1
Walker, H.D.M.2
-
7
-
-
0029254567
-
On correction of multiple design errors
-
February
-
I. Pomeranz and S. M. Reddy. On correction of multiple design errors. IEEE Trans. CAD, 14:255-264, February 1995.
-
(1995)
IEEE Trans. CAD
, vol.14
, pp. 255-264
-
-
Pomeranz, I.1
Reddy, S.M.2
-
8
-
-
0033711296
-
A technique for identifying rtl and gate-level correspondences
-
September
-
S. Ravi, I. Ghosh, V. Boppana, and N. K. Jha. A technique for identifying rtl and gate-level correspondences. International Conf. on Computer Design, pages 591-594, September 2000.
-
(2000)
International Conf. on Computer Design
, pp. 591-594
-
-
Ravi, S.1
Ghosh, I.2
Boppana, V.3
Jha, N.K.4
-
9
-
-
0032684766
-
A new method for diagnosing multiple stuck-at faults using multiple and single fault simulations
-
H. Takahashi, K. O. Boateng, and Y. Takamatsu. A new method for diagnosing multiple stuck-at faults using multiple and single fault simulations. Proc. IEEE VTS, pages 64-69, 1999.
-
(1999)
Proc. IEEE VTS
, pp. 64-69
-
-
Takahashi, H.1
Boateng, K.O.2
Takamatsu, Y.3
-
10
-
-
0033351758
-
Design error diagnosis and correction via test vector simulation
-
December
-
A. Veneris and I. N. Hajj. Design error diagnosis and correction via test vector simulation. IEEE Trans. CAD, 18(12):1803-1816, December 1999.
-
(1999)
IEEE Trans. CAD
, vol.18
, Issue.12
, pp. 1803-1816
-
-
Veneris, A.1
Hajj, I.N.2
-
12
-
-
0031378505
-
A deductive technique for diagnosis of bridging faults
-
S. Venkataraman and W. K. Fuchs. A deductive technique for diagnosis of bridging faults. Proc. IEEE ICCAD, pages 562-567, 1997.
-
(1997)
Proc. IEEE ICCAD
, pp. 562-567
-
-
Venkataraman, S.1
Fuchs, W.K.2
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