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Volumn , Issue , 2002, Pages 716-721

Incremental diagnosis and correction of multiple faults and errors

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN ERRORS; EXPONENTIAL COMPLEXITY; LOGIC DEBUGGING; MULTIPLE FAULTS; STUCK-AT FAULTS;

EID: 84893778198     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998378     Document Type: Conference Paper
Times cited : (22)

References (12)
  • 1
    • 0023829155 scopus 로고
    • Logic verification via test generation
    • January
    • M. S. Abadir, J. Ferguson, and T. E. Kirkland. Logic verification via test generation. IEEE Trans. CAD, 7:138-148, January 1988.
    • (1988) IEEE Trans. CAD , vol.7 , pp. 138-148
    • Abadir, M.S.1    Ferguson, J.2    Kirkland, T.E.3
  • 3
    • 0032319387 scopus 로고    scopus 로고
    • New techniques for deterministic test pattern generation
    • I. Hamzaoglu and J. H. Patel. New techniques for deterministic test pattern generation. Proc. IEEE VTS, pages 138-148, 1998.
    • (1998) Proc. IEEE VTS , pp. 138-148
    • Hamzaoglu, I.1    Patel, J.H.2
  • 4
    • 0142174913 scopus 로고    scopus 로고
    • Towards the logic defect diagnosis for partialscan designs
    • S. Y. Huang. Towards the logic defect diagnosis for partialscan designs. Proc. IEEE ASP-DAC, pages 313-318, 2001.
    • (2001) Proc. IEEE ASP-DAC , pp. 313-318
    • Huang, S.Y.1
  • 5
    • 0032595832 scopus 로고    scopus 로고
    • Errortracer: Design error diagnosis based on fault simulation techniques
    • September
    • S. Y. Huang and K. T. Cheng. Errortracer: Design error diagnosis based on fault simulation techniques. IEEE Trans. CAD, 18(9):1341-1352, September 1999.
    • (1999) IEEE Trans. CAD , vol.18 , Issue.9 , pp. 1341-1352
    • Huang, S.Y.1    Cheng, K.T.2
  • 6
    • 0032638330 scopus 로고    scopus 로고
    • Simulation-based error diagnosis and correction in combinational digital circuits
    • D. Nayak and D. M. H.Walker. Simulation-based error diagnosis and correction in combinational digital circuits. Proc. IEEE VTS, pages 70-78, 1999.
    • (1999) Proc. IEEE VTS , pp. 70-78
    • Nayak, D.1    Walker, H.D.M.2
  • 7
    • 0029254567 scopus 로고
    • On correction of multiple design errors
    • February
    • I. Pomeranz and S. M. Reddy. On correction of multiple design errors. IEEE Trans. CAD, 14:255-264, February 1995.
    • (1995) IEEE Trans. CAD , vol.14 , pp. 255-264
    • Pomeranz, I.1    Reddy, S.M.2
  • 9
    • 0032684766 scopus 로고    scopus 로고
    • A new method for diagnosing multiple stuck-at faults using multiple and single fault simulations
    • H. Takahashi, K. O. Boateng, and Y. Takamatsu. A new method for diagnosing multiple stuck-at faults using multiple and single fault simulations. Proc. IEEE VTS, pages 64-69, 1999.
    • (1999) Proc. IEEE VTS , pp. 64-69
    • Takahashi, H.1    Boateng, K.O.2    Takamatsu, Y.3
  • 10
    • 0033351758 scopus 로고    scopus 로고
    • Design error diagnosis and correction via test vector simulation
    • December
    • A. Veneris and I. N. Hajj. Design error diagnosis and correction via test vector simulation. IEEE Trans. CAD, 18(12):1803-1816, December 1999.
    • (1999) IEEE Trans. CAD , vol.18 , Issue.12 , pp. 1803-1816
    • Veneris, A.1    Hajj, I.N.2
  • 12
    • 0031378505 scopus 로고    scopus 로고
    • A deductive technique for diagnosis of bridging faults
    • S. Venkataraman and W. K. Fuchs. A deductive technique for diagnosis of bridging faults. Proc. IEEE ICCAD, pages 562-567, 1997.
    • (1997) Proc. IEEE ICCAD , pp. 562-567
    • Venkataraman, S.1    Fuchs, W.K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.