On efficient error diagnosis of digital circuits

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 678-687

  Sridhar, Nandini ^a   Hsiao, Michael S ^b  

^a INTEL CORPORATION   (United States)

^b VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BENCHMARKING; COMBINATORIAL CIRCUITS; ERROR DETECTION;

ERROR DIAGNOSIS;

DIGITAL CIRCUITS;

EID: 0035684002     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966688     Document Type: Article

References (21)

1. A fast algorithm for locating and correcting simple design errors in VLSI digital circuits
2. Multiple design error diagnosis and correction in digital VLSI circuits
3. Logic design verification via test generation
4. Logic design error diagnosis and correction
5. Diagnosis and correction of logic design errors in digital circuits
6. On diagnosis and correction of design errors
7. On error correction in macro-based circuits
8. An algorithm for locating logic design errors
9. Rectification of multiple logic design errors
10. Connection error location and correction in combinational circuits
11. Locating functional errors in logic circuits
12. Automating the diagnosis and rectification of design errors with PRIAM
13. Efficient automatic diagnosis of digital circuits
14. Error tracer: Design error diagnosis based on fault simulation techniques
15. A method for automatic design error location and correction in combinational logic circuits
16. Single gate design error diagnosis in combinational circuits
17. Modeling the unknown! towards model-independent fault and error diagnosis
18. Multiple error diagnosis based on xlists
19. Testing, verification, and diagnosis in the presence of unknowns
20. Error diagnosis of sequential circuits using region-based model
21. Restricted symbolic evaluation is fast and useful