Techniques to reduce data volume and application time for transition test

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 983-992

  Liu, Xiao ^a   Hsiao, Michael ^a   Chakravarty, Sreejit ^b   Thadikaran, Paul J ^b  

^a VIRGINIA POLYTECHNIC INSTITUTE AND STATE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DATA REDUCTION; MICROELECTRONIC PROCESSING; MICROPROCESSOR CHIPS; SCANNING;

APPLICATION TIME; CIRCUIT UNDER TEST; DATA VOLUME; EXCHANGE SCAN; TRANSITION TEST;

DESIGN FOR TESTABILITY;

EID: 0036445021     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2002.1041854     Document Type: Article

References (23)

1. I. Hamzaoglu and J. H. Patel "Compact Two-pattern Test Generation for Combinational and Full Scan Circuits," Proceedings of the International Test Conference, 1998.
2. B. Keller, C. Bamhart, V. Brunkhorst, F. Distler, A. Ferko, O. Farnsworth and B. Koenemann, "OPMISR: The Foundation of Compressed ATPG Vectors," IEEE International Test Conference, pp. 748-757, 2001.
3. I. Hamzaoglu and J. H. Patel, "Reducing test application time for full scan embedded cores," 29th International Symposium on Fault-Tolerant Computing, June 1999, pp. 260-267.
4. B. Koeneman, "LFSR-Coded Test Patterns for Scan Designs," IEEE European Test Conference, 1991, pp. 237-242.
5. A. Chandra and K. Chakrabarty, "Frequency directed run length (FDR) codes with application to system on a chip data compression," IEEE VLSI Test Symposium, 2001, pp. 42-47.
6. R.D. Eldred "Test Routing Based on Symbolic Logical Statement" Journal ACM, Vol.6 pp.33-36 Jan. 1959.
7. J. A. Waicukauski, E. Lindbloom, B. K. Rosen, and V. S. Iyengar. "Transition Fault Simulation," IEEE Design & Test of Computers, 4:32-38, 1987.
8. G.L. Smith "Model for Delay Faults based upon Paths," IEEE International Test Conference, pp. 342-349, 1985.
9. K. Heragu, J. H. Patel, and V. D. Agrawal, "Segment delay faults: a new fault model," IEEE VLSI Test Symposium, pp. 32-39, 1996.
10. M. L.Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal VLSI Circuits, Kluwer Academic Publishers, Boston, 2000.
11. J. Savir and S. Patil "On Broad-Side Delay Test," IEEE VLSI Test Symposium, pp.284-290, 1994.
12. J. Savir and S. Patil "Scan-Based Transition Test," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 8, 1993.
13. B. Dervisoglu and G. Stong "Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement," Proceedings of International Test Conference, pp.365-374, 1991.
14. I. Pormeranz and S. M. Reddy "Static Compaction for Two-Pattern Test Sets," IEEE Asian Test Symposium, pp.222-228, 1995.
15. L. N. Reddy, I. Pomeranz and S. M. Reddy "COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits," IEEE/ACM International Conference on Computer-Aided Design, pp.568-574, 1992.
16. F. F. Hsu, K. M. Butler and J. H. Patel, "A Case Study of the Illinois Scan Architecture," IEEE International Test Conference, 2001, pp. 538-547.
17. N. N. Tendulkar, R. F. Molyneaux, C. Pyron and R. Raina, "At-speed Scan Based Testing on MPC7400 Microprocessor," IEEE VLSI Test Symposium, pp. 3-8, 2000.
18. K. McCauley, "Scan is Good Enough for Stuck Faults, Why Not AC Scan for Delay Faults?" Panel position paper, IEEE International Test Conference, 2001, pp. 1172.
19. R. Raina, "AC-Scan: Microprocessors are ready But where is the Infrastructure?" Panel position paper, IEEE International Test Conference, 2001, pp. 1173.
20. S. Patil, "AC-Scan: Microprocessors are ready But where is the Infrastructure?" Panel position paper, IEEE International Test Conference, 2001, pp. 1174.
21. N. Tendulkar, R. Raina, R. Woltenburg, X. Lin, B. Swanson and G. Aldrich, "Novel Techniques for Achieving High At-Speed Transition Fault Coverage for Motorola's Microprocessors Based on PowerPC Instruction Set Architecture," IEEE VLSI Test Symposium, 2002, to appear.
22. K-J. Lee, J-J. Chen and C-H Huang, "Using a single input to support multiple scan chains," IEEE/ACM International Conference on Computer-Aided Design, 1998, pp. 74-78.
23. D. Das and N. A. Touba, "Reducing test data volume using external/LBIST hybrid test patterns," IEEE International Test Conference, 2000, pp. 115-122.