AC-Scan: Microprocessors are ready ... But where is the infrastructure?

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 1174-

  Patil, Srinivas ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; TIMING CIRCUITS; VECTORS;

DELAY FAULTS; FUNCTIONAL TESTS;

MICROPROCESSOR CHIPS;

EID: 0035687822     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)