Scan is good enough for stuck fault, why not AC scan for delay faults

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 1172-

  McCauley, Kevin ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COSTS; CRITICAL PATH ANALYSIS; TIMING CIRCUITS;

CLOCK GATING; STUCK FAULT TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0035687363     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)