Bulk-layout-compatible 0.18-μm SOI-CMOS technology using body-tied partial-trench-isolation (PTI)

IEEE Transactions on Electron Devices

Volumn 48, Issue 12, 2001, Pages 2816-2822

  Hirano, Yuuichi ^b   Maeda, Shigenobu ^b   Matsumoto, Takuji ^b   Nii, Koji ^b   Iwamatsu, Toshiaki ^b   Yamaguchi, Yasuo ^b   Ipposhi, Takashi ^b   Kawashima, Hiroshi ^b   Maegawa, Shigeto ^b   Inuishi, Masahide ^b   Nishimura, Tadashi ^a,b  

^a IEEE

^b MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

High speed integrated circuit; Isolation technology; Simulation; SOI technology; SRAM

Indexed keywords

COMPUTER SIMULATION; LEAKAGE CURRENTS; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; STATIC RANDOM ACCESS STORAGE; ULSI CIRCUITS;

HIGH-SPEED INTEGRATED CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0035694263     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.974709     Document Type: Article

References (19)

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14. Clarification of floating-body effects on current drivability in 0.18 μm partially depleted SOI MOSFETs
15. Bulk-layout-compatible 0.18 μm SOI CMOS technology by using partial-trench-isolation (PTI)
16. Low-voltage operation of a high-resistivity load SOI SRAM cell by reduced back-gate-bias effects
17. Analysis of the delay distributions of 0.5-μm SOI LSIs
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