0.2-μm bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processors

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1998, Pages 209-212

  Hashimoto, T ^a   Kikuchi, T ^a   Watanabe, K ^a   Ohashi, N ^a   Saito, T ^a   Yamaguchi, H ^a   Wada, S ^a   Natsuaki, N ^a   Kondo, M ^a   Kondo, S ^a   Homma, Y ^a   Owada, N ^a   Ikeda, T ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; BIPOLAR TRANSISTORS; BONDING; BUFFER STORAGE; COPPER; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; ION IMPLANTATION; METALLIZING; RANDOM ACCESS STORAGE; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS;

BIPOLAR JUNCTION TRANSISTORS (BJT); DEEP TRENCH ISOLATION (DTI); SHALLOW TRENCH ISOLATION (STI); STATIC RANDOM ACCESS MEMORY (SRAM);

CMOS INTEGRATED CIRCUITS;

EID: 17944404836     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)