Bulk-layout-compatible 0.18 μm SOI-CMOS technology using body-fixed partial trench isolation (PTI)

IEEE International SOI Conference

Volumn , Issue , 1999, Pages 131-132

  Hirano, Y ^a   Maeda, S ^a   Matsumoto, T ^a   Nii, K ^a   Iwamatsu, T ^a   Yamaguchi, Y ^a   Ipposhi, T ^a   Kawashima, H ^a   Maegawa, S ^a   Inuishi, M ^a   Nishimura, T ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; RANDOM ACCESS STORAGE; ULSI CIRCUITS;

FLOATING BODY EFFECTS; PARTIAL TRENCH ISOLATION (PTI) TECHNIQUE;

SILICON ON INSULATOR TECHNOLOGY;

EID: 17044450258     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)