Extraction of trap states at the oxide-silicon interface and grain boundary for polycrystalline silicon thin-film transistors

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 40, Issue 9 A, 2001, Pages 5227-5236

  Kimura, Mutsumi ^a   Nozawa, Ryoichi ^a   Inoue, Satoshi ^a   Shimoda, Tatsuya ^a   Lui, Basil On Kit ^b   Tam, Simon Wing Bun ^b   Migliorato, Piero ^c  

^a SEIKO EPSON CORPORATION   (Japan)

^b Epson Cambridge Laboratory   (United Kingdom)

^c UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

Capacitance voltage characteristic; Current voltage characteristic; Device simulation; Extraction; Grain boundary; Oxide silicon interface; Polycrystalline silicon; Potential barrier; Thin film transistor; Trap state

Indexed keywords

CARRIER CONCENTRATION; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRONIC DENSITY OF STATES; EXTRACTION; GRAIN BOUNDARIES; INTERFACES (MATERIALS); POLYSILICON; THIN FILM TRANSISTORS;

CAPACITANCE VOLTAGE CHARACTERISTICS; DEVICE SIMULATION; POTENTIAL DENSITY; TRAP STATES;

ELECTRON TRAPS;

EID: 0035456577     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.40.5227     Document Type: Article

References (63)