Grain boundary potential barrier inhomogeneities in low-pressure chemical vapor deposited polycrystalline silicon thin-film transistors

IEEE Transactions on Electron Devices

Volumn 44, Issue 9, 1997, Pages 1563-1565

  Dimitriadis, C A ^a  

^a ARISTOTLE UNIVERSITY OF THESSALONIKI   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL VAPOR DEPOSITION; ELECTRIC CONDUCTIVITY OF SOLIDS; GRAIN BOUNDARIES; POLYCRYSTALLINE MATERIALS; SEMICONDUCTING SILICON;

ARRHENIUS PLOTS; LOW PRESSURE CHEMICAL VAPOR DEPOSITION (LPCVD);

THIN FILM TRANSISTORS;

EID: 0031236218     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.622619     Document Type: Article

References (10)

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