CA-BIST for asynchronous circuits: A case study on the RAPPID asynchronous instruction length decoder

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2000, Pages 62-72

  Roncken, Marly ^a,b   Stevens, Ken ^a,b   Pendurkar, Rajesh ^c   Rotem, Shai ^a,b   Chaudhuri, Parimal Pal ^d  

^a INTEL CORPORATION   (United States)

^b INTEL CORPORATION   (Israel)

^c SUN MICROSYSTEMS   (United States)

^d INDIAN INSTITUTE OF ENGINEERING SCIENCE AND TECHNOLOGY   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS CIRCUITS; ASYNCHRONOUS DESIGN TECHNIQUES; ASYNCHRONOUS VERSION; CLOCKED CIRCUITS; DESIGN FOR TEST; DOMINO LOGIC; FAULT EFFECT; HARDWARE DESCRIPTIONS; NON-INVASIVE; ON CHIPS; PATTERN GENERATION; PENTIUM; PSEUDO RANDOM; STUCK-AT FAULTS; TEST PATTERN; TEST PATTERN GENERATIONS; TESTABILITY; UNTESTABLE FAULTS;

CELLULAR AUTOMATA; DECODING; DESIGN; PATTERN RECOGNITION SYSTEMS; RESEARCH;

BUILT-IN SELF TEST;

EID: 77957950144     PISSN: 15228681     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2000.836798     Document Type: Conference Paper

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