Timed circuit synthesis using implicit methods

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1999, Pages 181-188

  Thacker, Robert A ^a   Belluomini, Wendy ^a   Myers, Chris J ^a  

^a UNIVERSITY OF UTAH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; OPTIMIZATION; STATE SPACE METHODS; TIMING CIRCUITS;

TIMED CIRCUIT SYNTHESIS;

SEQUENTIAL CIRCUITS;

EID: 0032755191     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icvd.1999.745146     Document Type: Conference Paper

References (17)