Defect-oriented testability for asynchronous IC's

Proceedings of the IEEE

Volumn 87, Issue 2, 1999, Pages 363-375

  Roncken, Marly ^a,b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b INTEL CORPORATION   (United States)

Author keywords

Asynchronous circuits; Bridging faults; DfT; IDDQ; Self timed; Stuck at faults; Testability

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

DESIGN FOR TEST (DFT);

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 0033080339     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.740029     Document Type: Article

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