Design methodology for the S/390 Parallel Enterprise Server G4 microprocessors

IBM Journal of Research and Development

Volumn 41, Issue 4-5, 1997, Pages 515-546

  Shepard, K L ^a   Carey, S M ^a   Cho, E K ^a   Curran, B W ^a   Hatch, R F ^a   Hoffman, D E ^a   McCabe, S A ^a   Northrop, G A ^a   Seigler, R ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; LOGIC DESIGN; PARALLEL PROCESSING SYSTEMS;

TRANSISTOR LEVEL CUSTOM DESIGN APPROACH;

MICROPROCESSOR CHIPS;

EID: 0031175711     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.414.0515     Document Type: Article

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