A Shallow Trench Isolation using LOCOS Edge for Preventi.ng Corner Effects for 0.25/0.18prn CMOS Technologies and Beycmd

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 829-832

  Chatterjee, A ^a   Rogers, D ^a   McKee, J ^a   Ali, I ^a   Nag, S ^a   Chen, I C ^a  

^a Semiconduct Proc Des Ctr T   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOW NOISE AMPLIFIERS; DIODES; ETCHING; INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS; MOS DEVICES; OXIDES; TRANSISTORS;

CMOS TECHNOLOGY; CORNER EFFECTS; DIODE LEAKAGE; NARROW-WIDTH EFFECTS; OXIDE RELIABILITY; SHARP CORNERS; SUBTHRESHOLD CHARACTERISTICS; TRANSISTOR WIDTH; TRENCH ETCH; TRENCH ISOLATION;

CMOS INTEGRATED CIRCUITS;

LOCOS TECHNOLOGY; NMOS DEVICE; PMOS DEVICE; SHALLOW TRENCH ISOLATION; SHARP CORNER EFFECTS;

EID: 0030383520     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.554107     Document Type: Conference Paper

References (7)

1. [l]C. Koburger, et al, 1994 VLSI Tech., pp.85
2. M. Bohr, et al, IEDM Tech. Dig., pp.273, 1994
3. A. H. Perera, et al, IEDM Tech. Dig., pp.679, 1995
4. A. Bryant, et al, IEDM Tech. Dig., pp.671, 1994.
5. T. Park, et aZ, IEDM Tech. Dig., pp.675, 1994
6. K. Ishimaru, et al, 1994 VLSI Tech., pp.97
7. A. Chatterjee, et al, 1996 VLSI Tech., pp.156