Inversion channel edge in trench-isolated sub-l/4-μm MOSFET's

IEEE Transactions on Electron Devices

Volumn 43, Issue 8, 1996, Pages 1274-1280

  Vandervoorn, P J ^a   Krusius, J P ^a  

^a Cornell University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRONS; FINITE ELEMENT METHOD; MOSFET DEVICES; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; THREE DIMENSIONAL;

DRIFT DIFFUSION EQUATION; POISSON EQUATION; SHORT CHANNEL EFFECT; THRESHOLD VOLTAGE; TRENCH EDGE EFFECT;

CMOS INTEGRATED CIRCUITS;

EID: 0030214550     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.506779     Document Type: Article

References (21)

1. A. Bryant, W. Haensch, and Toshio Mii, "Characteristics of CMOS device isolation for the ULSI age," IEDM Tech. Dig., pp. 671-674, 1994.
2. I. Chen, M. Rodder, A. Chatterjee, and C. Teng, "A trench isolatian study for deep submicron CMOS technology," VLSITSA, pp. 251-255, 1993.
3. A. Bryant, W. Haensch, S. Geissler, J. Mandelman, D. Poindexter, and M. Steger, "The current-carrying corner inherent to trench isolation," IEEE Electron Device Lett., vol. 14, no. 8, pp. 412-414, Aug. 1993.
4. K. Shibihara, Y. Fujimoto, M. Ilamada, S. Iwao, K. Tokashiki, aid T. Kunio, "Trench isolation with nabla-shaped buried oxide for 256 Mega-bit drams," IEDM Tech. Dig., pp. 275-278, 1992.
5. K. One, S. Odanaka, K. Moriyama, T. Hori, and G. Fuse, "Narrowwidth effects of shallow îrench-isoîated CMOS with n"polysilicon gate," IEEE Trans. Electron Devices, vol. 36, no. 6, pp. 1110-1115, June 1989.
6. G. Fuse, M. Fukumoto, A. Shinohara, S. Odanaka, M. Sasago, and T. Ohzone, "A new isolation method with boron-implanted sidewalls lor controlling narrow-width effect," IEEE Trans. Electron Devices, vol. ED-34, no. 2, pp. 356-359, Dec. 1987.
7. H. Inokawa, Y. Yamamoto. Y. Okazaki, T. Kobayashi, M. Miyaké, and H. Ishii, "Ultranarrow trench-isolated 0.2-μm CMOS and its application to ultralow-power frequency dividers," IEDM Tech. Dig., pp. 887-890, 1993.
8. B. Davari, C. Kohurger, T. Furukawa, Y. Taur, W. Noble, A. Megdanis, J. Warnock, and J. Mauer, "A variable-size shallow trench isolation (STI) technology with diffused sidcwall doping for submicron CMOS," IEDM Tech. Dig., pp. 92-95, 1988.
9. K. K.-L. Hsueh, J. Sanchez. T. A. Demassa, and L. A. Akers, "Inversenarrow-width effects and small-geometry MOSFRT threshold voltage model," IEEE Trans. Electron Devices, vol. 35, no. 3, pp. 325-338, Mar. 1988.
10. N. Shigyo, S. Fukuda, T. Wada, K. Hicda, T. Hamamoto, H. Watanabe, K. Sunouchi, and H. Tango, "Three-dimensional analysis of subthreshold swing and transconductance for fully recessed oxide (trench) isolated l/4-//m-width MOSFET's," IEEE Trans. Electron Devices, vol. 35, no. 7, pp. 945-951, July 1988.
11. N. Shigyo and R. Dang, "Analysis of an anomalous subthreshold current in a fully recessed oxide MOSFET using a three-dimensional device simulator," IEEE Trans. Electron Devices, vol. ED-32, no. 2. pp. 441-445, Feb. 1985.
12. ]12J T. lizuka, K. Y. Chiu, and J. L. Moll, "Double threshold MOSFET's in birds's-beak free structures," IEDM Tech. Dig., pp. 380-383, 1981.
13. W. Lee, S. E. Laux, M. V. Fischetti, G. Baccarini, A. Gnudi, J. M. C. Stork, J. A. Mandelman, E. F. Crabbé, M. R. Wordeman, and F. Odeh, "Numerical modeling of advanced semiconductor devices," IBM J. Res. Develop., vol. 36, no. 2, pp. 208-230, Mar. J992.
14. K. Hess, J. P. Eeburton, and U. Ravaioli, Computational Electronics: Semiconductor Transport and Device Simulation. Boston: Kluwer, 1990, pp. 10-11.
15. L. A. Akers, M. Sugino, and J. M. Ford, "Characterization of inversenarrow-width effect," IEEE Trans. Electron Devices, vol. ED-34, no. 12, pp. 2476-2484, Dec. 1987.
16. S. S.-S. Chung and T.-C. Li, "An analytical threshold-voltage model of trench-isolated MOS devices with nonuniformly doped substrates," IEEE Trans. Electron Devices, vol. 39, no. 3, pp. 614-622, Mar. 1992.
17. E. H. Li, K. M. Hong, Y. C. Cheng. and K. Y. Chan, "The narrowchannel effect in MOSFET's with semi-recessed oxide structures," IEEE Trans. Electron Devices, vol. 37, no. 3, pp. 692-701, Mar. 1990.
18. ] 18] Thunder is a Three-Dimensional Device Simulator, Silvaco International, Santa Clara, CA.
19. S. E. Laux, M. V. Fischetti, and D. J. Frank, "Monte Carlo analysis of semiconductor devices: The Damocles program," IBM J. Research Develop., vol. 34. no. 4, pp. 466-494, July 1990.
20. B. Davari, W.-H. Chang, K. E. Petrillo, C. Y. Wong, D. Moy, Y. Taur, M, R. Wordeman. J. Y.-C. Sun, C. C.-H. Hsu, and M. R. Polcari, "A high performance 0.25-/im CMOS technology: U-Technology," IEEE Trans. Electron Devices, vol. 39, pp. 967-975, Apr. 1992.
21. G. G. Shahidi, J. Warnock, S. Fischer, P. A. McFarland, A. Acovic, S. Subbanna, E. Ganin, E. Crabbé, J. Comfort, J. Y.-C. Sun, T. Ning, and B. Divari, "High-performance devices for a 0.15-4m CMOS technology," IEEE Electron Device Lett, vol. 14, pp. 466-4-68, Oct. 1993.