Impact of super-steep-retrograde channel doping profiles on the performance of scaled devices

IEEE Transactions on Electron Devices

Volumn 46, Issue 8, 1999, Pages 1711-1717

  De Indranil, ^a   Osburn, Carlton M ^b  

^a IEEE   (United States)

^b NORTH CAROLINA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MOS DEVICES; MOSFET DEVICES; QUANTUM THEORY; THRESHOLD VOLTAGE;

CHANNEL ENGINEERING; SATURATION CURRENT; SHORT CHANNEL EFFECTS; SUBTHRESHOLD; SUPER STEEP RETROGRADED CHANNELS; UNIFORMLY DOPED MOSFET;

SEMICONDUCTOR DOPING;

EID: 0033169530     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.777161     Document Type: Article

References (24)

1. K. F. Yee and C. M. Osburn, Response surface based optimization of 0.1 fj,m NMOSFET's with thin gate dielectrics, in Proc. TECHCON, 1998
2. C. H. Wann, K. Noda, T. Tanaka, M. Yoshida, and C. Hu, A com- parative study of advanced MOSFET concepts, IEEE Trans. Electron Devices, vol. 43, p. 1742, Oct. 1996
3. J. A. Lopez-Villanueva, F. Gamiz, J. B. Roldan, Y. Ghailan, J. E Carcellar, and P. Cartujo, Study of effects of a stepped doping profile in short-channel MOSFET's, IEEE Trans. Electron Devices, vol. 44, p. 1425, Sept. 1997
4. G. G. Shahidi, D. A. Antoniadis, and H. I. Smith, Indium channel implant for improved short-channel behavior of submicrometer NMOS- FET's, IEEE Trans. Electron Devices, vol. 14, p. 409, Aug. 1993.
5. K. Noda, T. Uchida, T. Tatsumi, T. Aoyama, H. Miyamoto, and I. Sasaki, 0.1 ftm delta-doped MOSFET using post low-energy implanting selective epitaxy, in Proc. Symp. VLSI Technol., 1996, p. 19.
6. R. Kircher, J. Moruta, M. Foruno, K. Aizawa, M. Kato, A. Horinouchi, and S. Ono, In-situ doping of epitaxial silicon by low-temperature LPCVD for the fabrication of delta-doped MOSFET's, in Proc. Int. Conf. SSDM, 1991, p. 672
7. M. Aoki et al., Design and performance of 0.1 /j,m CMOS devices using low-impurity channel transistors, IEEE Electron Device Lett., vol. 13, p. 50, Jan. 1992
8. K. Yamaguchi, Y. Shiraki, Y. Katayama, and Y. Muriyama, A new short-channel MOSFET with an atomic-layer-doping impurity profile, Jpn. J. Appl. Phys., vol. 22, pp. 267-270, 1983
9. W. H. Chang, L. K. Wang, and R. A. Wachnik, Latch-up studies in 0.5 micron gate CMOS technology with retrograde n-well, in Proc. 1st Int. Symp. ULSI Sci. Technol., 1987, p. 80
10. G. G. Shahidi, D. A. Antoniadis, and H. I. Smith, Electron velocity overshoot at room and liquid nitrogen temperatures in silicon inversion layers, IEEE Trans. Electron Devices, vol. 9, p. 94, Feb. 1988
11. B. Agrawal, V. K. De, and J. D. Meindl, Device parameter optimization for reduced short-channel effects in retrograde doping MOSFET's, IEEE Trans. Electron Devices, vol. 43, p. 365, Feb. 1996
12. S. Venkatesan, J. W. Lutze, C. Lage, and W. J. Taylor, Device drive current degradation observed with retrograde channel profiles, in IEDM Tech. Dig., 1995, p. 419
13. T. Skotnicki and P. Bouillon, Electrical performances of retrograde versus conventional profile MOSFET's, in Proc. Symp. VLSI Technol., 1996, p. 152
14. National Technology Roadmap for Semiconductors, Semiconductor In- dustry Assoc., San Jose, CA, 1997
15. ATLAS 4.0, Silvaco Int., Santa Clara, CA
16. H. Shin, A. F. Tasch, C. M. Maziar, and S. K. Bannerjee, A new approach to verify and derive a tranverse field dependent mobility model for electrons in MOS inversion layers, IEEE Trans. Electron Devices, vol. 36, pp. 1117-1123, June 1989
17. V. M. Agostinelli, H. Shin, and A. F. Tasch, A comprehensive model for inversion layer hole mobility for simulation for submicrometer MOSFET's, IEEE Trans. Electron Devices, vol. 38, pp. 151-159, Jan. 1991
18. UTQUANT2.0, Univ. Texas, Austin
19. Z. Liu, C. Hu, J. Huang, T. Chan, M. Jeng, P. K. Ko, and Y. C. Cheng, Threshold voltage model for deep-submicrometer MOSFET's, IEEE Trans. Electron Devices, vol. 40, pp. 86-94, Jan. 1993
20. M. J. Van Dort, P. H. Woerlee, and A. J. Walker, A simple model for quantization effects in heavily-doped silicon MOSFET's at inversion conditions, Solid State Electron., vol. 37, p. 411, 1994.
21. R. Sitte, S. Dimitrijev, and H. B. Harrison, Device parameter change caused by manufacturing fluctuations of deep submicron MOSFET's, IEEE Trans. Electron Devices, vol. 41, pp. 2210-2215, Nov. 1994.
22. X. Tang, V. K. De, and J. D. Meindl, Effects of random MOSFE parameter fluctuations on total power consumption, in Proc. 1996 Int Symp. Low Power Electron. Des., pp. 233-236.
23. K. Takeuchi, T. Tatsumi, and A. Furukawa, Channel engineering fo the reduction of random-dopant-placement-induced threshold voltag fluctuation, in 1EDM Tech. Dig., 1997, p. 841.
24. J. R. Brews, Sensitivity of subthreshold current to profile variations i long-channel MOSFET's, IEEE Trans. Electron Devices, vol. 43, pp 2164-2171, Dec. 1996.