Indium Channel Implant for Improved Short-Channel Behavior of Submicrometer NMOSFET's

IEEE Electron Device Letters

Volumn 14, Issue 8, 1993, Pages 409-411

  Shahidi, G G ^a   Davari, Bijan ^a   Bucelot, Thomas J ^a   Ronsheim, P A ^b   Coane, P J ^a   Pollack, S ^a   Blair, C R ^a   Clark, B ^b   Hansen, Howard H ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BORON; CMOS INTEGRATED CIRCUITS; SEMICONDUCTING INDIUM;

BORON-IMPLANTED SHORT-CHANNEL MOSFETS; INDIUM CHANNEL IMPLANT; SHORT-CHANNEL EFFECT (SCE); SUBMICROMETER NMOSFETS;

MOSFET DEVICES;

EID: 0027641506     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.225595     Document Type: Article

References (9)

1. T. Ohzone, H. Shimura, K. Tsuji, and T. Hirao, “Silicon gate n-well CMOS process by full ion implantation technology,” IEEE Trans. Electron Devices, vol. ED-27, p. 1789, 1980.
2. G. G. Shahidi, D. A. Antoniadis, and H. I. Smith, “Electron velocity overshoot at room and liquid nitrogen temperatures in silicon inversion layers,” IEEE Electron Device Lett., vol. 9, p. 94, 1988.
3. G. G. Shahidi, D. A. Antoniadis, and H. I. Smith, “Indium channel implant for improved device behaviour in deep sub-micron regime,” in DRC Tech. Dig., 1989, p. 94.
4. M. Aoki et al., “0.1 μm CMOS devices using low-impurity-channel transistors,” in IEDM Tech. Dig., 1990, p. 939.
5. R. H. Yan et al., “High performance 0.1-μm room temperatures Si MOSFET's,” in Dig. Tech. Papers, 1992 Symp. VLSI Tech., 1992, p. 86.
6. D. A. Antoniadis and I. Moskowtiz, “Diffusion of indium in silicon, in inert and oxidizing ambients,” J. Appl. Phys., vol. 53, no. 12, p. 9214, 1982.
7. B. Davari et al., “A high performance 0.25 μm CMOS technology,” in IEDM Tech. Dig., 1988, p. 56.
8. C. F. Machala, III, P. C. Pattnaik, and P. Yang, “An efficient algorithm for extraction of parameters with high confidence from nonlinear models,” in Proc. IEEE Work Shop Test Structures, Feb. 17, 1986.
9. W. H. Chang et al., “A high performance 0.25-μm CMOS technology: I—Design and characterization,” IEEE Trans. Electron Devices, vol. 39, p. 959, 1992.