메뉴 건너뛰기




Volumn 13, Issue 1, 1992, Pages 50-52

Design and Performance of 0.1-μm CMOS Devices Using Low-Impurity-Channel Transistors (LICT's)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTALS - EPITAXIAL GROWTH; INTEGRATED CIRCUITS, VLSI; LITHOGRAPHY - ELECTRON BEAM; SEMICONDUCTOR DEVICES, MOS;

EID: 0026742666     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.144948     Document Type: Article
Times cited : (43)

References (5)
  • 1
    • 84941448723 scopus 로고
    • Design and experimental technology for 0:1-μm gatelength low-temperature operation FET's
    • G.A. Sai-Halasz et al., “Design and experimental technology for 0:1-μm gatelength low-temperature operation FET's,” IEEE Electron Device Lett., vol. EDL-8, p. 463, 1987.
    • (1987) IEEE Electron Device Lett. , vol.8 EDL , pp. 463
    • Sai-Halasz, G.A.1
  • 2
    • 0006405069 scopus 로고
    • Three-dimensional device simulator CADDETH with highly convergent matrix solution algorithms
    • T. Toyabe, H. Masuda, Y. Aoki, H. Shukuri, and T. Hagiwara, “Three-dimensional device simulator CADDETH with highly convergent matrix solution algorithms,” IEEE Trans. Electron Devices, vol. ED-32, p. 2038, 1985.
    • (1985) IEEE Trans. Electron Devices , vol.32 ED , pp. 2038
    • Toyabe, T.1    Masuda, H.2    Aoki, Y.3    Shukuri, H.4    Hagiwara, T.5
  • 3
    • 0024750814 scopus 로고
    • Fabrication of deep sub-μm narrow-channel Si-MOSFET's with twofold-gate structures
    • T. Yoshimura et al., “Fabrication of deep sub-μm narrow-channel Si-MOSFET's with twofold-gate structures,” Japan. J. Appl. Phys., vol. 28, p. 2183, 1989.
    • (1989) Japan. J. Appl. Phys. , vol.28 , pp. 2183
    • Yoshimura, T.1
  • 4
    • 36549099479 scopus 로고
    • Sub-100-nm p+- n shallow junctions fabricated by group III dual ion implantation and rapid thermal annealing
    • C-M. Lin, A.J. Steckl, and T.P. Chow, “Sub-100-nm p+- n shallow junctions fabricated by group III dual ion implantation and rapid thermal annealing,” Appl. Phys. Lett., vol. 54, p. 1790, 1989.
    • (1989) Appl. Phys. Lett. , vol.54 , pp. 1790
    • Lin, C.M.1    Steckl, A.J.2    Chow, T.P.3
  • 5
    • 0023112558 scopus 로고
    • Performance and hot-carrier effects of small CRYO-CMOS devices
    • M. Aoki, S. Hanamura, T. Masuhara, and K. Yano, “Performance and hot-carrier effects of small CRYO-CMOS devices,” IEEE Trans. Electron Devices, vol. ED-34, p. 8, 1987.
    • (1987) IEEE Trans. Electron Devices , vol.34 ED , pp. 8
    • Aoki, M.1    Hanamura, S.2    Masuhara, T.3    Yano, K.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.