A fast nonenumerative automatic test pattern generator for path delay faults

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 7, 1999, Pages 1050-1057

  Tragoudas, S ^a   Karayiannis, D ^a  

^a University of Arizona   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; ESTIMATION; FAILURE ANALYSIS; PROBABILITY;

AUTOMATIC TEST PATTERN GENERATION; FAULT COVERAGE; PATH DELAY FAULTS;

INTEGRATED CIRCUIT TESTING;

EID: 0032691216     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.771185     Document Type: Article

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