Synthesis of delay fault testable combinational logic

Volumn , Issue , 1989, Pages 418-421

  Roy, Kaushik ^a   Abraham, Jacob A ^a   De, Kaushik ^a   Lusky, Stephen ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING LANGUAGES--LISP; INTEGRATED CIRCUIT TESTING;

BLOCKED PATHS; COMBINATIONAL LOGIC; DELAY FAULT TESTABILITY; DON'T CARE TERMS; FANOUT; MULTILEVEL CIRCUIT;

LOGIC CIRCUITS, COMBINATORIAL;

EID: 0024889675     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)