NEST: A Nonenumerative Test Generation Method for Path Delay Faults in Combinational Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 14, Issue 12, 1995, Pages 1505-1515

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a   Uppaluri, Prasanti ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DELAY CIRCUITS; ERROR DETECTION; ESTIMATION; FAILURE ANALYSIS; MATHEMATICAL MODELS; OPTIMIZATION; POLYNOMIALS; SET THEORY;

FAULT SIMULATION METHOD; NONENUMERATIVE TEST GENERATION METHOD; PATH DELAY FAULTS;

COMBINATORIAL CIRCUITS;

EID: 0029547554     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.476581     Document Type: Article

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