833 Mb/s 2.5 V 4 Mb double data rate SRAM

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 356-357,-464

  Park, H C ^a   Yang, S K ^a   Jung, M C ^a   Kang, T G ^a   Kim, S C ^a   Sohn, K M ^a   Bae, D G ^a   Kim, S S ^a   Kim, K H ^a   Sohn, B S ^a   Kim, H S ^a   Byun, H G ^a   Shin, Y S ^a   Lim, K H ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BUFFER STORAGE; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DATA REDUCTION; DATA TRANSFER; ELECTRIC CURRENT CONTROL; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); MICROPROCESSOR CHIPS; TIMING CIRCUITS;

ASYNCHRONOUS DYNAMIC TO STATIC CONVERTERS (ADSC); AUTO TRACKING BITLINE (ATB); BLOCK SELECT LINES (BSL); DOUBLE DATA RATE STATIC RANDOM ACCESS MEMORY (DDR SRAM); READ ADDRESS REGISTERS (RAR); READ COUNTERS (RC); SORTED READ DATA REGISTERS (SRDR); SORTED WRITE DATA REGISTERS (SWDR); WRITE ADDRESS REGISTERS (WAR); WRITE COUNTERS (WC);

RANDOM ACCESS STORAGE;

EID: 0031654069     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)