400MHz 4.5Mb synchronous BiCMOS SRAM with alternating bit-line loads

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 146-147

  Suzuki, Azuma ^a   Kobayashi, Tomohiro ^a   Hamano, Takahiro ^a   Hatada, Hiroshi ^a   Kawasumi, Atsushi ^a   Matsuoka, Fumitomo ^a   Ishimaru, Kazunari ^a   Takahashi, Minoru ^a   Nishigohri, Masahito ^a   Okayama, Yasunori ^a   Unno, Yukari ^a   Kakumu, Masakazu ^a   Tsujimoto, Jun ichi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BIPOLAR TRANSISTORS; BUFFER STORAGE; CLOCKS; CMOS INTEGRATED CIRCUITS; ELECTRIC DELAY LINES; ELECTRIC WAVEFORMS; PIPELINE PROCESSING SYSTEMS; SHIFT REGISTERS; TIMING CIRCUITS;

ALTERNATING BIT LINE LOADS; BIT LINE DELAY; CHIP MICROGRAPH; PIPELINE REGISTER; SKEW COMPENSATED WRITE; SWITCHED DELAY DECODER;

RANDOM ACCESS STORAGE;

EID: 0030087403     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)