A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 10, 1996, Pages 1443-1448

  Higeta, Keiichi ^a,b   Usami, Masami ^a   Ohayashi, Masayuki ^a   Fujimura, Yasuhiro ^a   Nishiyama, Masahiko ^a   Isomura, Satoru ^a   Yamaguchi, Kunihiko ^a   Idei, Youji ^a   Nambu, Hiroaki ^a   Ohhata, Kenichi ^a   Hanta, Nadateru ^a  

^a HITACHI LTD   (Japan)

^b WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC VARIABLES MEASUREMENT; EMITTER COUPLED LOGIC CIRCUITS; ERRORS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; LOGIC GATES; SILICON ON INSULATOR TECHNOLOGY;

MEMORY CELL TEST TECHNIQUE; ON CHIP TEST CIRCUITRY; SOFT ERROR IMMUNE MEMORY CELL;

RANDOM ACCESS STORAGE;

EID: 0030269514     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.540054     Document Type: Article

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