3.6 mW 1.4 V SRAM with non-boosted, vertical bipolar bitline contact memory cell

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 352-353,-463

  Sato, H ^a   Nagaoka, H ^a   Honda, H ^a   Maki, Y ^a   Wada, T ^a   Arita, Y ^a   Tsutsumi, K ^a   Yamada, M ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ENERGY DISSIPATION; MOSFET DEVICES; SEMICONDUCTOR DIODES; SPURIOUS SIGNAL NOISE; TIMING CIRCUITS; VOLTAGE CONTROL;

BIPOLAR BITLINE CONTACT (BBC) MEMORY CELLS; STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0031683266     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)