2ns zero wait state, 32kB semi-associative L1 cache

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 154-155

  Covino, Jim ^a   Connor, John ^a   Evans, Don ^a   Roberts, Alan ^a   Robillard, Marcel ^a   Sousa, Jose ^a   Temullo Jr , Luigi ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVE STORAGE; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; COMPUTER ARCHITECTURE; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; PIPELINE PROCESSING SYSTEMS;

DATA STORAGE ARRAY; DATA UNIT CONTROLS; FIXED POINT UNIT; MEMORY BUILT-IN SELF TEST;

BUFFER STORAGE;

EID: 0030081470     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)