350 MHz 3.3 V 4 Mb SRAM fabricated in a 0.3 μm CMOS process

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 40, Issue , 1997, Pages 404-405

  Braceras, Geordie ^a   Evans, Donald ^a   Sousa, Jose ^a   Connor, John ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA TRANSFER; DIFFERENTIAL AMPLIFIERS; ELECTRIC POWER SUPPLIES TO APPARATUS; FIELD EFFECT TRANSISTORS; INTERCONNECTION NETWORKS; NAND CIRCUITS; PULSE WIDTH MODULATION; RANDOM ACCESS STORAGE; SPURIOUS SIGNAL NOISE; TIMING CIRCUITS; VOLTAGE REGULATORS;

STATIC RANDOM ACCESS MEMORY (SRAM); TIMING PROTOCOLS;

MICROPROCESSOR CHIPS;

EID: 0031070116     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)