1V 100MHz 10mW cache using separated bit-line memory hierarchy and domino tag comparators

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 152-153

  Mizuno, Hiroyuki ^a   Matsuzaki, Nozomu ^a   Osada, Kenichi ^a   Shinbo, Toshinobu ^a   Ooki, Nagatoshi ^a   Ishida, Hiroshi ^a   Ishibashi, Koichiro ^a   Kure, Tokuo ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; COMPUTER SIMULATION; ELECTRIC WAVEFORMS; SCHEMATIC DIAGRAMS; SEMICONDUCTOR SWITCHES;

DOMINO TAG COMPARATORS; HIERARCHY SWITCHES; SEPARATED BIT LINE MEMORY HIERARCHY; TRACE SIMULATION; WAY SWITCHES;

BUFFER STORAGE;

EID: 0030083460     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)