Charge transfer amplifier and an encoded bus architecture for low power SRAM

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1997, Pages 77-78

  Kawashima, Shoichiro ^a   Mori, Toshihiko ^a   Sasagawa, Ryuhei ^a   Hamaminato, Makoto ^a   Wakayama, Shigetoshi ^a   Sukegawa, Kazuo ^a   Fukushi, Isao ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC LOSSES; INTEGRATED CIRCUIT MANUFACTURE; MOSFET DEVICES; RANDOM ACCESS STORAGE;

BUS SIGNAL ENCODING SCHEME; CHARGE TRANSFER (CT) AMPLIFIERS; STATIC RANDOM ACCESS MEMORY (SRAM);

AMPLIFIERS (ELECTRONIC);

EID: 0031384338     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)