500 MHz 4 Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 40, Issue , 1997, Pages 406-407

  Nakamura, Kazuyuki ^a   Takeda, Koichi ^a   Toyoshima, Hideo ^a   Noda, Kenji ^a   Ohkubo, Hiroaki ^a   Uchida, Tetsuya ^a   Shimizu, Toshiyuki ^a   Itani, Toshiro ^a   Tokashiki, Ken ^a   Kishimoto, Koji ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; INPUT OUTPUT PROGRAMS; LOGIC GATES; MICROPROCESSOR CHIPS; MOSFET DEVICES; PIPELINE PROCESSING SYSTEMS; SEQUENTIAL SWITCHING; SIGNAL ENCODING; SPURIOUS SIGNAL NOISE;

CENTRAL PROCESSING UNIT (CPU); DOUBLE LATE WRITE BUFFERS (DLWB); PREFETCHED PIPELINE BURST (PPB); STATIC RANDOM ACCESS STORAGE (SRAM);

RANDOM ACCESS STORAGE;

EID: 0031074718     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)