Post-stress interface trap generation induced by oxide-field stress with FN injection

IEEE Transactions on Electron Devices

Volumn 45, Issue 9, 1998, Pages 1972-1977

  Chen, T P ^a,b   Li, Stella ^a   Fung, S ^a   Baling, C D ^a   Lo, K F ^a  

^a UNIVERSITY OF HONG KONG   (Hong Kong)

^b CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

Author keywords

Integrated circuit reliability; Mos devices; Mosfet's; Semiconductor device reliability; Silicon materials devices

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; FUNCTION GENERATORS; HOT CARRIERS; OXIDES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR JUNCTIONS;

CHARGE PUMPING MEASUREMENT; HOT CARRIER STRESS; INTEGRATED CIRCUIT RELIABILITY; SEMICONDUCTOR DEVICE RELIABILITY; SEMICONDUCTOR PARAMETER ANALYZER;

MOSFET DEVICES;

EID: 0032166006     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.711363     Document Type: Article

References (17)

1. R. Bellens, E. der Schrijver, G. Van den bosch, G. Groeseneken, P. Heremans, and H. E. Maes, On the hole-carrier-induced post-stress interface trap generation in n-channel MOS transistor, IEEE Trans. Electron Devices, vol. 41, p. 413, 1994.
2. E. de Schrijver, P. Heremans, R. Bellens, G. Groeseneken, and H. Maes, Post-stress interface trap generation: A new hot carrier induced degradation phenomenon in passivated n-channel MOSFET's, in Proc. Int. Reliability Phys. Symp., 1992, p. 112.
3. R. S. Scott, N. A. Dumin, T. W. Hughes, D. J. Dumin, and B. T. Moore, Properties of high-voltage stress generated traps in thin silicon oxide, IEEE Trans. Electron Devices, vol. 43, p. 1133, July 1996.
4. Y. Hokari, Stress voltage polarity dependence of thermally grown thin gate oxide wearout, IEEE Trans. Electron Devices, vol. 35, p. 1299, 1988.
5. D. J. Dumin, S. K. Mopuri, S. Vanchinathan, R. S. Scott, R. Subramoniam, and T. G. Lewis, High field related thin oxide wearout and breakdown, IEEE Trans. Electron Devices, vol. 42, p. 760, 1995.
6. E. Rosenbaum, Z. Liu, and C. Hu, Silicon dioxide breakdown lifetime enhancement under bipolar bias conditions, IEEE Trans. Electron Devices, vol. 40, p. 2287, 1993.
7. -, The effects of oxide stress waveform on MOSFET performance, in IEDM Tech. Dig., 1991, p. 719.
8. P. Chaparala, J. S. Suehle, C. Messick, and M. Roush, Electric field dependent dielectric breakdown of intrinsic SiC>2 films under dynamic stress, in Proc. IRPS. 1996, p. 61.
9. D. J. Dumin, K. Dickerson, M. Hall, W. Vigrass, and G. A. Brown, Correlation of wearout and breakdown in sub-10 nm silicon oxide, in Tech. Dig. IEDM. 1988, p. 718.
10. C. Hu, S. C. Tarn, F. C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Terrill, Hot-electron-induced MOSFET degradation-model, monitor and improvement, IEEE Trans. Electron Devices, Vol. ED32, p. 375, 1985.
11. P. Heremans, R. Bellens, G. Groeseneken, and H. E. Maes, Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFET's, IEEE Trans. Electron Devices, vol. 35, p. 2194, 1988.
12. E. Takeda, A. Shimizu, and T. Hagiwara, Role of hot-hole injection in hot-carrier effects and the small degraded channel in MOSFET's, IEEE Electron Device Lett., Vol. EDL4, p. 329, 1983.
13. N. S. Saks and D. B. Brown, Interface trap formation via the two-stage H+ process, IEEE Trans. Nucl. Sci., vol. 36, p. 1848, Dec. 1989.
14. A. G. Revesz, Chemical and structural aspects of the irradiation behavior of SiO2 films on silicon, IEEE Trans. Nucl. Sci., vol. NS-24, p. 2102, 1977.
15. D. J. DiMaria, E. Cartier, and D. A. Buchanan, Anode hole injection and trapping in silicon dioxide, J. Appl. Phys., vol. 80, p. 304, 1996.
16. D. J. DiMaria, E. Cartier, and D. Arnold, Impact ionization, trap creation, degradation, and breakdown in silicon dioxide films on silicon, J. Appl. Phys.. vol. 73, p. 3367, 1993.
17. D. J. DiMaria, Defect production, degradation, and breakdown of silicon dioxide films, Solid-State Electron., vol. 41, p. 957, 1997.