Charge collection in submicron cmos/soi technology

IEEE Transactions on Nuclear Science

Volumn 44, Issue 6 PART 1, 1997, Pages 2124-2133

  Musseau, Q ^a,b   Ferlet Cavrois, V ^b   Knudson, A R ^c   Stapor, W J ^d   McDonald, P T ^a   Pelloie, J L ^b   Raynaud, C ^c  

^a CEA DIF   (France)

^b NAVAL RESEARCH LABORATORY   (United States)

^c SFA INC   (United States)

^d CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CMOS INTEGRATED CIRCUITS; ELECTRIC CHARGE MEASUREMENT; RADIATION EFFECTS; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; SPECTROSCOPIC ANALYSIS;

BIPOLAR MECHANISM; CHARGE COLLECTION SPECTROSCOPY; DRAIN JUNCTIONS; SINGLE EVENT UPSET (SEU); SOURCE JUNCTIONS; STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0031344026     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.659027     Document Type: Article

References (18)

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