Parasitic Bipolar Gain in Fully Depleted n-Channel SOI MOSFET’s

IEEE Transactions on Electron Devices

Volumn 41, Issue 6, 1994, Pages 970-977

  Ver Ploeg, Eric P ^a   Nguyen, Cuong T ^b   Plummer, James D ^c   Wong, S Simon ^c  

^a HITACHI LTD   (Japan)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^c STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR SEMICONDUCTOR DEVICES; COMMUNICATION CHANNELS (INFORMATION THEORY); GAIN MEASUREMENT; IONIZATION; MATHEMATICAL MODELS; PARAMETER ESTIMATION; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY;

BIPOLAR GAIN; BODY DOPING CONCENTRATION; DRAIN VOLTAGE; FLOATING BASE; PARASITIC LATERAL BIPOLAR STRUCTURE;

MOSFET DEVICES;

EID: 0028448743     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.293310     Document Type: Article

References (18)

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