Optimizing quarter and sub-quarter micron cmos circuit speed considering interconnect loading effects

IEEE Transactions on Electron Devices

Volumn 44, Issue 9, 1997, Pages 1556-1558

  Chen, Kai ^a   Hu, Chenming ^a   Fang, Peng ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); OSCILLATORS (ELECTRONIC); SEMICONDUCTOR DEVICE MODELS;

RING OSCILLATORS;

CMOS INTEGRATED CIRCUITS;

EID: 0031234005     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.622616     Document Type: Article

References (6)

1. K. Chen, C. H. Wann, P. K. Ko, and C. Hu, "The impact of device scaling and power supply change on CMOS gate performance," IEEE Electron Device Lett., vol. 17, pp. 202-204, May 1996.
2. S.-Y. Oh and K.-J. Chang, "2001 needs for multilevel interconnect technology," Circuits Devices Mag., Jan. 1995.
3. M. T. Bohr, "Interconnect scaling - The real limiter to high-performance ULSI," Solid-State Technol., pp. 105-111, Sept. 1996.
4. K. Chen, H. C. Wann, J. Duster, M. Yoshida, P. K. Ko, and C. Hu, "MOSFET carrier mobility model based on gate oxide thickness, threshold, and gate voltages," J. Solid-State Electron., vol. 39, no. 10, pp. 1515-1518, Oct. 1996.
5. K. Chen, C. Hu, P. Fang, and A. Gupta, "Experimental confirmation of an accurate CMOS gate delay model for gate oxide and voltage scaling," IEEE Electron Device Lett., vol. 18, pp. 275-277, June 1997.
6. T. Kuroi, S. Shimizu, S. Ogino, A. Teramoto, M. Shirahata, Y. Okumura, M. Inuishi, and H. Miyoshi, "Sub-quarter-micron dual gate CMOSFET's with ultrathin gate oxide of 2 nm," in Symp. VLSI Technol. Dig. Tech. Papers Japan, 1996, pp. 210-211.