Experimental confirmation of an accurate CMOS gate delay model for gate oxide and voltage scaling

IEEE Electron Device Letters

Volumn 18, Issue 6, 1997, Pages 275-277

  Chen, Kai ^a,b   Hu, Chenming ^a,b   Fang, Peng ^a,c   Gupta, Ashawant ^a,c  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENT MEASUREMENT; GATES (TRANSISTOR); MOSFET DEVICES; OXIDES; SEMICONDUCTOR DEVICE MODELS; THICKNESS MEASUREMENT; VOLTAGE MEASUREMENT;

GATE PROPAGATION DELAY;

OSCILLATORS (ELECTRONIC);

EID: 0031163242     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.585355     Document Type: Article

References (5)

1. K. Chen, H. C. Wann, J. Duster, M. Yoshida, P. K. Ko, and C. Hu, "MOSFET carrier mobility model based on gate oxide thickness, threshold and gate voltages," J. Solid-State Electron., vol. 39, no. 10, pp. 1515-1518, 1996.
2. K. Chen, H. C. Wann, J. Duster, D. Pramanik, S. Nariani, P. K. Ko, and C. Hu, "An accurate semi-empirical saturation drain current model for LDD N-MOSFET," IEEE Electron Device Lett., vol. 17, pp. 145-147, Mar. 1996.
3. K. Chen, H. C. Wann, P. K. Ko, and C. Hu, "The impact of device scaling and power supply change on CMOS gate performance," IEEE Electron Device Lett., vol. 17, pp. 202-204, May 1996.
4. K. F. Schuegraf, C. C. King, and C. Hu, "Ultra-thin silicon dioxide leakage current and scaling limit," Symp. VLSI Technol., Dig. Tech. Papers, sect. 3-1, pp. 18-19, 1992.
5. C. Hu, "Device and technology impact on low power electronics", in Low-Power Design Methodologies, J. M. Rabaey and M. Pedram, Eds. Norwell, MA: Kluwer, 1995, pp. 21-36.