Polysilicon gate depletion effect on IC performance

Solid State Electronics

Volumn 38, Issue 11, 1995, Pages 1975-1977

  Chen, Kai ^a   Chan, Mansun ^a   Ko, Ping K ^a   Hu, Chenming ^a   Huang, Jian Hui ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; EFFECTS; ELECTRIC INVERTERS; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; MOS DEVICES; PERFORMANCE; PERMITTIVITY; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING;

CAPACITANCE-VOLTAGE CHARACTERISTICS; POLYSILICON GATE DEPLETION; RING-OSCILLATORS; VOLTAGE DROP;

GATES (TRANSISTOR);

EID: 0029408467     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/0038-1101(95)00108-6     Document Type: Article

References (6)

1. + Polysilicon in a dual-gate MOS process
2. Investigation of the physical modeling of the gate-depletion effect