An accurate semi-empirical saturation drain current model for LDD N-MOSFET

IEEE Electron Device Letters

Volumn 17, Issue 3, 1996, Pages 145-147

  Chen, Kai ^b   Wann, H Clement ^b   Duster, Jon ^b   Pramanik, Dipankar ^a,c   Nariani, Subhash ^a,c   Ko, Ping K ^a,b   Hu, C ^a,b  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

^c PHILIPS RESEARCH LABORATORIES   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; ELECTRIC VARIABLES MEASUREMENT; GATES (TRANSISTOR); MOSFET DEVICES; SEMICONDUCTOR DEVICE STRUCTURES;

ELECTRON MOBILITY; MOBILITY DEGRADATION; SEMIEMPIRICAL SATURATION MODEL; SOURCE DRAIN SERIES RESISTANCE; VELOCITY SATURATION;

SEMICONDUCTOR DEVICE MODELS;

EID: 0030108265     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.485195     Document Type: Article

References (2)

1. K. Chen, H. C. Wann, J. Duster, M. Yoshida, P. K. Ko, and C. Hu, "Universal MOSFET's carrier mobility model solely dependent on gate oxide thickness, threshold voltage and gate bias," submitted to IEEE Electron Device Lett.
2. P. K. Ko, "Approaches to scaling," in VLSI Electronics: Microstructure Science, Vol. 18, New York: Academic, 1989, pp. 1-37.