BSIM: Berkeley Short-Channel IGFET Model for MOS Transistors

IEEE Journal of Solid-State Circuits

Volumn 22, Issue 4, 1987, Pages 558-566

  Sheu, Bing J ^a   Scharfetter, Donald L ^a,b   Ko, Ping Keung ^a   Jeng, Min Chie ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Automated Characterization Systems Inc ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

TRANSISTORS - MATHEMATICAL MODELS;

BERKELEY SHORT-CHANNEL IGFET MODEL (BSIM); SIMULATION PROGRAM WITH INTEGRATED CIRCUIT EMPHASIS; SPICE;

SEMICONDUCTOR DEVICES, MOS;

EID: 0023401686     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1987.1052773     Document Type: Article

References (34)

1. L. W. Nagel, “SPICE2: A computer program to simulate semiconductor circuits,” Electron. Res. Lab., Univ. of Calif., Berkeley, Memo ERL-M520, May 1975.
2. R. A. Saleh, J. E. Kleckner, and A. R. Newton, “Iterated timing analysis and SPLICE1,” presented at the IEEE Int. Conf. computer-Aided Design, Santa Clara, CA., Sept. 1983.
3. J. White and A. Sangiovanni-Vincentelli, “RELAX2: A new wave-form relaxation approach for the analysis of LSI MOS circuits,” presented at the IEEE Int. Symp. Circuits and Systems, Newport Beach, Ca, May 1983.
4. J. T. Deutsch and A. R. Newton, “A multiprocessor implementation of relaxation-based electrical circuit simulation,” presented at the ACM/IEEE 21st Design Automation Conf., Albuquerque, NM, June 1984.
5. J. T. Deutsch, “Algorithms and architecture for multiprocessor-based circuit simulation,” Electron. Res. Lab., Univ. of Calif., Berkeley, Memo ERL-M85/39, May 1985.
6. A. Vladimirescu and S. Liu, “The simulation of MOS integrated circuits using SPICE2,” Electron. Res. Lab., Univ. of Calif., Berkeley, Memo ERL-M80/7, Oct. 1980.
7. H. K. J. Ihantola and J. L. Moll, “Design theory of a surface effect transistor,” Solid-State Electron., vol. 7, 423–430, June 1964.
8. H. C. Pao and C. T. Sah, “Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors (MOST),” Solid-State Electron., vol. 9, 927–937, 1966.
9. Y. A. El-Mansy, “Modeling of Insulated-gate field-effect transistors,” Ph.D. dissertation, Carleton Univ., Ottawa, Ont., Canada, Nov. 1974.
10. J. R. Brews, “A charge-sheet model of the MOSFET,” Solid-State Electron., vol. 21, 345–355, 1978.
11. R. M. Swanson and J. D. Meindl, “Ion-implanted complementary MOS transistor in low voltage circuits,” IEEE J. Solid-State Circuits, vol. SC-7, pp. 146–153, Apr. 1972.
12. R. R. Troutman, “Subthreshold design considerations for IGFETs,” IEEE J. Solid-State Circuits, vol. SC-9, no. 2, pp. 55–60, Apr. 1974.
13. G. W. Taylor, “Subthreshold conduction in MOSFET,” IEEE Trans. Electron Devices, vol. ED-25, vol. 3, 337–350, Mar. 1978.
14. G. W. Taylor, “A unified device model for a short-channel MOSFET,” presented at the IEEE 39th Annual Device Research 1981.
15. W. Fichtner, “Three-dimensional numerical modeling of small-size MOSFET’s,” presented at the IEEE 39th Annual Device Research Conf., 1981.
16. S. Liu, “A unified CAD model for MOSFETs,” Electron. Res. Lab., Univ. of Calif., Berkeley, Memo ERL-M81/31, May 1981.
17. H. C. Poon, private communication, 1979.
18. S. Liu and L. W. Nagel, “Small-signal MOSFET models for analog circuit ‘design,” IEEE J. Solid-State Circuits, vol. SC-17, no. 6, pp. 983–998, Dec. 1982.
19. B. J. Sheu, D. L. Scharfetter, and H. C. Poon, “Compact short-channel IGFET model (CSIM),” Electron. Res. Lab., Univ. of Calif., Berkeley, Memo ERL-M84/20, Mar. 1984.
20. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 2nd ed. New York: Wiley, 1984, p. 63.
21. D. A. Hodges and H. G. Jackson, Analysis and Design of Digital Integrated Circuits. New York: McGraw-Hill, 1983, p. 47.
22. P. Antognetti, D. D. Cavigia, and E. Profumo, “CAD model for threshold and subthreshold conduction in MOSFETs,” IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp. 454–458, June 1982.
23. A. H.-C. Fung, “A subthreshold conduction model for BSIM,” Electron. Res. Lab., Univ. of Calif., Berkeley, Memo. ERL-M85/22, Mar. 1985.
24. K. Doganis and D. L. Scharfetter, “General optimization and extraction of IC device model parameters,” IEEE Trans. Electron Devices, vol. ED-30, no. 9, pp. 1219–1228, Sept. 1983.
25. D. E. Ward and K. Doganis, “Optimized extraction of MOS model parameters,” IEEE Trans. Computer-Aided Des., vol. CAD-1, no. 4, pp. 163–168, Oct. 1982.
26. E. Khalily, P. H. Decher, and D. A. Teegarden, “TECAP: An interactive device characterization and model development system,” in Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1984, pp. 149–151.
27. P. Yang and P. K. Chatteijee, “An optimal parameter extraction program for MOSFET models,” IEEE Trans. Electron Devices, vol. ED-30, no. 9, pp. 1214–1219, Sept. 1983.
28. N. Herr, B. Garbs, and J. J. Barnes, “A statistical modeling approach for simulation of MOS VLSI circuit designs,” in IEDM Tech. Dig., 1982, pp. 290–293.
29. P. Yang and P. Chatteijee, “Statistical modeling of small geometry MOSFETs,” in IEDM Tech. Dig., 1982, 286–289.
30. P. Cox, P. Yang, S. S. Mahant-Shetti, and P. K. Chatteijee, “Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits,” IEEE Trans. Electron Devices, vol. ED-32, no. 2, pp. 471–478, Feb. 1985.
31. M.-C. Jeng, B. J. Sheu, P. K. Ko, and D. L. Scharfetter, “Parameter extraction for Berkeley short-channel IGFET model (BSIM),” in preparation.
32. B. J. Sheu, D. L. Scharfetter, and P. K. Ko, “SPICE2 implementation of BSIM,” Electron. Res. Lab., Univ. of Calif., Berkeley, Memo ERL-M85/42, May 1985.
33. B. J. Sheu, “MOS transistor modeling and characterization for circuit simulation,” Ph.D. dissertation, Electron. Res. Lab., Univ. of Calif., Berkeley, Memo ERL-M85/22, Oct. 1985.
34. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley-Interscience, 1981, p. 46.