A physical model for MOSFET output resistance

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1992-December, Issue , 1992, Pages 569-572

  Huang, J H ^a   Liu, Z H ^a   Jeng, M C ^a,b   Ko, P K ^a   Hu, C ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DRAIN CURRENT; MOSFET DEVICES;

ANALOG APPLICATIONS; CHANNEL LENGTH MODULATION; DEVICE PARAMETERS; DRAIN-INDUCED BARRIER LOWERING; GATE OXIDE THICKNESS; HOT CARRIER EFFECT; OUTPUT RESISTANCE; SHORT-CHANNEL EFFECT;

ELECTRIC RESISTANCE;

EID: 49749131836     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1992.307426     Document Type: Conference Paper

References (8)

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3. K. Toh, et al, "An engineering Model for Short-Channel MOS Devices, " IEEE J. Solid-state Circuits, vol. 23, No. 4, Aug. 1988.
4. Z. H. Liu, et al. "Threshold Voltage Model For Deep-Submicrometer MOSFETs, " IEEE Tran. Electron Devices. In press.
5. C. Hu, et al, IEEE Tran. Electron Devices, vol. ED-32, p375, Feb. 1985.
6. M. C. Jeng, "Design and Modeling of Deep-Submicrometer MOSFETs, " Ph. D. Dissertation, Univ. of California, Berkeley, 1990.
7. P. Gray and R. Meyer, "Analysis and Design of Analog Integrated Circuits, " 2nd Edition.
8. Sodini, et al, IEEE Tran. Electron Devices, vol. ED-31, No. 10, p. 1386, Oct. 1984.