메뉴 건너뛰기




Volumn 10, Issue 3, 1991, Pages 376-389

A Charge Sheet Capacitance Model of Short Channel MOSFET's for SPICE

Author keywords

[No Author keywords available]

Indexed keywords

BAND STRUCTURE; ELECTRIC MEASUREMENTS - CAPACITANCE; ELECTRIC WAVEFORMS; INTEGRATED CIRCUITS, DIGITAL; OSCILLATORS;

EID: 0026128884     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.67791     Document Type: Article
Times cited : (66)

References (50)
  • 1
    • 0009703767 scopus 로고
    • Design theory of a surface field effect transistor
    • June
    • H. K. Ihantola and J. L. Moll, “Design theory of a surface field effect transistor,” Solid-State Electron., vol. 7, pp. 423–430, June 1964.
    • (1964) Solid-State Electron. , vol.7 , pp. 423-430
    • Ihantola, H.K.1    Moll, J.L.2
  • 2
    • 49949134400 scopus 로고
    • Effects of diffusion current on characteristics of metal-oxide (insulator)—semiconductor transistors
    • H. C. Pao and C. T. Sah, “Effects of diffusion current on characteristics of metal-oxide (insulator)—semiconductor transistors,” Solid-State Electron., vol. 9, no. 10, pp. 927–937, 1966.
    • (1966) Solid-State Electron. , vol.9 , Issue.10 , pp. 927-937
    • Pao, H.C.1    Sah, C.T.2
  • 3
    • 84937744575 scopus 로고
    • Modeling and simulation of insulated-gate field effect transistor switching circuits
    • Sept.
    • H. Schichman and D. A. Hodges, “Modeling and simulation of insulated-gate field effect transistor switching circuits,” IEEE J. Solid-State Circuits, vol. SC-3, pp. 265–289, Sept. 1968.
    • (1968) IEEE J. Solid-State Circuits , vol.SC-3 , pp. 265-289
    • Schichman, H.1    Hodges, D.A.2
  • 4
    • 0015330654 scopus 로고
    • Ion-implanted complementary MOS transistor in low voltage circuits
    • Apr.
    • R. M. S. Swanson and J. D. Meindl, “Ion-implanted complementary MOS transistor in low voltage circuits,” IEEE J. Solid-State Circuits, vol. SC-7, pp. 146–153, Apr. 1972.
    • (1972) IEEE J. Solid-State Circuits , vol.SC-7 , pp. 146-153
    • Swanson, R.M.S.1    Meindl, J.D.2
  • 5
    • 0015346472 scopus 로고
    • An accurate large-signal MOS transistor model for use in computer-aided-design
    • May
    • G. Merckel, J. Borel, and N. Z. Cupcea, “An accurate large-signal MOS transistor model for use in computer-aided-design,” IEEE Trans. Electron. Devices, vol. ED-19, pp. 681–690, May 1972.
    • (1972) IEEE Trans. Electron. Devices , vol.ED-19 , pp. 681-690
    • Merckel, G.1    Borel, J.2    Cupcea, N.Z.3
  • 7
    • 0017932965 scopus 로고
    • A charge-sheet model of the MOSFET
    • J. R. Brews, “A charge-sheet model of the MOSFET,” Solid-State Electron., vol. 21, pp. 345–355, 1978.
    • (1978) Solid-State Electron. , vol.21 , pp. 345-355
    • Brews, J.R.1
  • 8
    • 0018754251 scopus 로고
    • A long-channel MOSFET model
    • F. Van de Wiele, “A long-channel MOSFET model,” Solid-State Electron., vol. 22, pp. 991–997, 1979.
    • (1979) Solid-State Electron. , vol.22 , pp. 991-997
    • van de Wiele, F.1
  • 10
  • 11
    • 0020291970 scopus 로고
    • Small-signal MOSFET models for analog circuit design
    • Dec.
    • S. Liu and L. W. Nagel, “Small-signal MOSFET models for analog circuit design,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 983–998, Dec. 1982.
    • (1982) IEEE J. Solid-State Circuits , vol.SC-17 , pp. 983-998
    • Liu, S.1    Nagel, L.W.2
  • 12
    • 0020191751 scopus 로고
    • SPICE modeling for small geometry MOSFET circuits
    • P. Yang and P. K. Chatteijee, “SPICE modeling for small geometry MOSFET circuits,” IEEE Trans. Computer-Aided Design, vol. CAD-1, pp. 169–182, 1982.
    • (1982) IEEE Trans. Computer-Aided Design , vol.CAD-1 , pp. 169-182
    • Yang, P.1    Chatteijee, P.K.2
  • 13
    • 0020708861 scopus 로고
    • Simplified long channel MOSFET theory
    • R. F. Pierret and J. A. Shields, “Simplified long channel MOSFET theory,” Solid-State Electron., vol. 26, no. 2, pp. 143–147, 1983.
    • (1983) Solid-State Electron. , vol.26 , Issue.2 , pp. 143-147
    • Pierret, R.F.1    Shields, J.A.2
  • 14
    • 0021195518 scopus 로고
    • The theory of long channel MOSFET
    • A. Nussbaum, R. Sinha, and D. Dokos, “The theory of long channel MOSFET,” Solid-State Electron., vol. 27, no. 1, pp. 97–106, 1984.
    • (1984) Solid-State Electron. , vol.27 , Issue.1 , pp. 97-106
    • Nussbaum, A.1    Sinha, R.2    Dokos, D.3
  • 15
    • 0023401686 scopus 로고
    • BSIM: Berkeley short channel IGFET model for MOS transistors
    • Aug.
    • B. J. Sheu, D. L. Scharfetter, P. K. Ko, and M. C. Jeng, “BSIM: Berkeley short channel IGFET model for MOS transistors,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 558–566, Aug. 1987.
    • (1987) IEEE J. Solid-State Circuits , vol.SC-22 , pp. 558-566
    • Sheu, B.J.1    Scharfetter, D.L.2    Ko, P.K.3    Jeng, M.C.4
  • 17
    • 0003879668 scopus 로고    scopus 로고
    • Physics and Technology of Semiconductor Devices
    • New York: Wiley
    • A. S. Grove, Physics and Technology of Semiconductor Devices. New York: Wiley, 1967.
    • Grove, A.S.1
  • 18
    • 0004005306 scopus 로고    scopus 로고
    • Physics of Semiconductor Devices
    • 2nd ed., ch. 7
    • S. Sze, Physics of Semiconductor Devices, 2nd ed., 1981, ch. 7.
    • Sze, S.1
  • 19
    • 0003805738 scopus 로고    scopus 로고
    • Device Electronics for Integrated Circuits
    • New York: Wiley
    • R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits. New York: Wiley, 1977.
    • Muller, R.S.1    Kamins, T.I.2
  • 20
    • 84914396658 scopus 로고    scopus 로고
    • Theory and Application of FET's
    • New York: Wiley
    • R. S. C. Cobbold, Theory and Application of FET's. New York: Wiley, 1970, pp. 272–304.
    • Cobbold, R.S.C.1
  • 21
    • 0015025121 scopus 로고
    • MOS models and circuit simulation
    • J. E. Meyer, “MOS models and circuit simulation,” RCA Rev., vol. 32, pp. 42–63, 1971.
    • (1971) RCA Rev. , vol.32 , pp. 42-63
    • Meyer, J.E.1
  • 22
    • 0018027059 scopus 로고
    • A charge-oriented model for MOS transistor capacitances
    • D. E. Ward and R. W. Dutton, “A charge-oriented model for MOS transistor capacitances,” IEEE J. Solid-State Circuits, vol. SC-13, no. 5, pp. 703–708, 1978.
    • (1978) IEEE J. Solid-State Circuits , vol.SC-13 , Issue.5 , pp. 703-708
    • Ward, D.E.1    Dutton, R.W.2
  • 23
  • 24
    • 0020193283 scopus 로고
    • A description of MOS internodal capacitances for transient simulations
    • Oct.
    • G. W. Taylor, W. Fichtner, and I. G. Simmons, “A description of MOS internodal capacitances for transient simulations,” IEEE Trans. Computer-Aided Design, vol. CAD-1, pp. 150–156, Oct. 1982.
    • (1982) IEEE Trans. Computer-Aided Design , vol.CAD-1 , pp. 150-156
    • Taylor, G.W.1    Fichtner, W.2    Simmons, I.G.3
  • 25
    • 0020267716 scopus 로고
    • A complete large and small signal charge model for an MOS transistor
    • R. L. Conilogue and C. Viswanathan, “A complete large and small signal charge model for an MOS transistor,” in IEEE IEDM 82 Tech. Dig., 1982, pp. 654–657.
    • (1982) IEEE IEDM 82 Tech. Dig. , pp. 654-657
    • Conilogue, R.L.1    Viswanathan, C.2
  • 26
    • 0020593385 scopus 로고
    • A simple charge-based model for MOS transistor capacitances: A new production tool
    • Jan.
    • G. I. Serhan and S. Y. Yu, “A simple charge-based model for MOS transistor capacitances: A new production tool,” IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 48–51, Jan. 1983.
    • (1983) IEEE Trans. Computer-Aided Design , vol.CAD-2 , pp. 48-51
    • Serhan, G.I.1    Yu, S.Y.2
  • 27
    • 0020834178 scopus 로고
    • On the small-signal behavior of the MOS transistor in quasistatic operation
    • C. Turchetti, G. Masetti, and Y. Tsividis, “On the small-signal behavior of the MOS transistor in quasistatic operation,” Solid-State Electronics, vol. 26, no. 10, pp. 941–949, 1983.
    • (1983) Solid-State Electronics , vol.26 , Issue.10 , pp. 941-949
    • Turchetti, C.1    Masetti, G.2    Tsividis, Y.3
  • 29
    • 0022009051 scopus 로고
    • A charge-based large-signal model for thin-film SOI MOSFET's
    • Feb.
    • H. K. Lim and J. G. Fossum, “A charge-based large-signal model for thin-film SOI MOSFET's,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 366–377, Feb. 1985.
    • (1985) IEEE J. Solid-State Circuits , vol.SC-20 , pp. 366-377
    • Lim, H.K.1    Fossum, J.G.2
  • 30
    • 0022795975 scopus 로고
    • Table lookup MOSFET capacitance model for short-channel devices
    • Oct.
    • T. Shima, “Table lookup MOSFET capacitance model for short-channel devices,” IEEE Trans. Computer-Aided Design, vol. CAD-5, pp. 624–632, Oct. 1986.
    • (1986) IEEE Trans. Computer-Aided Design , vol.CAD-5 , pp. 624-632
    • Shima, T.1
  • 31
    • 0022956814 scopus 로고
    • A measurement based charge sheet capacitance model of short channel MOSFETs for SPICE
    • Dec.
    • H. J. Park, P. K. Ko, and C. Hu, “A measurement based charge sheet capacitance model of short channel MOSFETs for SPICE,” in IEEE IEDM 86 Tech. Dig., Dec. 1986, pp. 40–43.
    • (1986) IEEE IEDM 86 Tech. Dig. , pp. 40-43
    • Park, H.J.1    Ko, P.K.2    Hu, C.3
  • 32
    • 0024091521 scopus 로고
    • A physical parametric transistor model for CMOS circuit simulation
    • Oct.
    • S. Yu, A. F. Franz, and T. G. Mihran, “A physical parametric transistor model for CMOS circuit simulation,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 1038–1052, Oct. 1988.
    • (1988) IEEE Trans. Computer-Aided Design , vol.7 , pp. 1038-1052
    • Yu, S.1    Franz, A.F.2    Mihran, T.G.3
  • 33
    • 0020193819 scopus 로고
    • On-chip capacitance measurement circuits in VLSI structures
    • Oct.
    • H. Iwai and S. Kohyama, “On-chip capacitance measurement circuits in VLSI structures,” IEEE Trans. Electron. Devices, vol. ED-29, pp. 1622–1626, Oct. 1982.
    • (1982) IEEE Trans. Electron. Devices , vol.ED-29 , pp. 1622-1626
    • Iwai, H.1    Kohyama, S.2
  • 34
    • 0021640119 scopus 로고
    • Characterization of intrinsic capacitances of small-geometry MOSFET's
    • Sept.
    • B. J. Sheu, P. K. Ko, and F. C. Hsu, “Characterization of intrinsic capacitances of small-geometry MOSFET's,” in IEEE 1984 Symp. VLSI Technology Tech. Digest, Sept. 1984, pp. 80–81.
    • (1984) IEEE 1984 Symp. VLSI Technology Tech. Digest , pp. 80-81
    • Sheu, B.J.1    Ko, P.K.2    Hsu, F.C.3
  • 35
    • 0022009440 scopus 로고
    • A scalable technique for the measurement of intrinsic MOS capacitances with atto-farad resolution
    • Feb.
    • H. Iwai, J. E. Oristian, J. T. Walker, and R. W. Dutton, “A scalable technique for the measurement of intrinsic MOS capacitances with atto-farad resolution,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 264–276, Feb. 1985.
    • (1985) IEEE J. Solid-State Circuits , vol.SC-20 , pp. 264-276
    • Iwai, H.1    Oristian, J.E.2    Walker, J.T.3    Dutton, R.W.4
  • 36
    • 0342637501 scopus 로고
    • Measurement of minimum geometry MOS transistor capacitances
    • Feb.
    • J. J. Paulos and D. A. Antoniadis, “Measurement of minimum geometry MOS transistor capacitances,” IEEE Trans. Electron. Devices, vol. ED-32, pp. 357–363, Feb. 1985.
    • (1985) IEEE Trans. Electron. Devices , vol.ED-32 , pp. 357-363
    • Paulos, J.J.1    Antoniadis, D.A.2
  • 37
    • 0022737474 scopus 로고
    • Measurement and modeling of short-channel MOS transistor gate capacitances
    • June
    • B. J. Sheu and P. K. Ko, “Measurement and modeling of short-channel MOS transistor gate capacitances,” in IEEE J. Solid State Circuits, vol. SC-22, pp. 464–472, June 1987.
    • (1987) IEEE J. Solid State Circuits , vol.SC-22 , pp. 464-472
    • Sheu, B.J.1    Ko, P.K.2
  • 38
    • 0021787638 scopus 로고
    • A direct measurement technique for small geometry MOS transistor capacitances
    • Jan.
    • K. C.-K. Weng and P. Yang, “A direct measurement technique for small geometry MOS transistor capacitances,” IEEE Electron. Device Lett., vol. EDL-6, pp. 40–42, Jan. 1985.
    • (1985) IEEE Electron. Device Lett. , vol.EDL-6 , pp. 40-42
    • Weng, K.C.-K.1    Yang, P.2
  • 39
    • 84941603742 scopus 로고
    • Measurement and modeling of small-geometry MOS transistor capacitances, private communication through his
    • Dept. of EECS, Massachusetts Institute of Technology, Aug.
    • J. J. Paulos, private communication through his Ph.D. dissertation, “Measurement and modeling of small-geometry MOS transistor capacitances,” VLSI Memo No. 84–199, Dept. of EECS, Massachusetts Institute of Technology, Aug. 1984.
    • (1984) Ph.D. dissertation, VLSI Memo No 84–199
    • Paulos, J.J.1
  • 40
    • 0003540106 scopus 로고    scopus 로고
    • Computer Aided Analysis of Electronic Circuits
    • Englewood Cliffs, NJ: Prentice Hall
    • L. O. Chua and P. M. Lin, Computer Aided Analysis of Electronic Circuits. Englewood Cliffs, NJ: Prentice Hall, 1975.
    • Chua, L.O.1    Lin, P.M.2
  • 41
    • 0003915801 scopus 로고
    • SPICE2: A computer program to simulate semiconductor circuits
    • Univ. of California, Berkeley, CA May 9
    • L. W. Nagel, “SPICE2: A computer program to simulate semiconductor circuits,” ERL-Memo. M520, Electronics Research Lab., Univ. of California, Berkeley, CA May 9, 1975.
    • (1975) ERL-Memo. M520, Electronics Research Lab
    • Nagel, L.W.1
  • 43
    • 0003478555 scopus 로고    scopus 로고
    • Applied Numerical Analysis, 2nd Ed
    • Reading, MA: Addison-Wesley
    • C. F. Gerald, Applied Numerical Analysis, 2nd Ed. Reading, MA: Addison-Wesley, 1978.
    • Gerald, C.F.1
  • 44
    • 0003494616 scopus 로고    scopus 로고
    • An Introduction to Splines for use in Computer Graphics and Geometric Modeling
    • Morgan Kaufmann, Ch. 3
    • R. H. Bartels, J. C. Beatty, and B. A. Barsky, An Introduction to Splines for use in Computer Graphics and Geometric Modeling. Morgan Kaufmann, 1987, Ch. 3.
    • Bartels, R.H.1    Beatty, J.C.2    Barsky, B.A.3
  • 45
    • 0018683243 scopus 로고
    • Characterization of the electron mobility in the inverted 〈100 〉Si surface
    • A. G. Sabnis and J. T. Clemens, “Characterization of the electron mobility in the inverted 〈100 〉Si surface,” in IEEE Int. Electron Devices Meeting, Tech. Dig., pp. 18–21, 1979.
    • (1979) IEEE Int. Electron Devices Meeting, Tech. Dig. , pp. 18-21
    • Sabnis, A.G.1    Clemens, J.T.2
  • 46
    • 84917975891 scopus 로고    scopus 로고
    • IEEE Trans. Electron. Devices
    • D. Frohman-Bentchkowsky, and A. S. Grove, IEEE Trans. Electron. Devices, vol. ED-16, p. 108, 1969.
    • , vol.ED-16 , pp. 108
    • Frohman-Bentchkowsky, D.1    Grove, A.S.2
  • 47
    • 0000573172 scopus 로고
    • A CAD-oriented non-quasistatic approach for the transient analysis of MOS IC's
    • C. Turchetti, P. Mancini, and G. Masetti, “A CAD-oriented non-quasistatic approach for the transient analysis of MOS IC's,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 827–836, 1986.
    • (1986) IEEE J. Solid-State Circuits , vol.SC-21 , pp. 827-836
    • Turchetti, C.1    Mancini, P.2    Masetti, G.3
  • 48
    • 0020269013 scopus 로고
    • A simple model for the overlap capacitance of a VLSI MOS device
    • R. Shrivastava and K. Fitzpatrick, “A simple model for the overlap capacitance of a VLSI MOS device,” IEEE Trans. Electron Devices, vol. ED-29, pp. 1870–1872, 1982.
    • (1982) IEEE Trans. Electron Devices , vol.ED-29 , pp. 1870-1872
    • Shrivastava, R.1    Fitzpatrick, K.2
  • 49
    • 0023310714 scopus 로고
    • Analysis of velocity saturation and other effects on short-channel MOS transistor capacitances
    • Mar.
    • H. Iwai, M. R. Pinto, C. R. Rafferty, J. E. Oristian, and R. W. Dutton, “Analysis of velocity saturation and other effects on short-channel MOS transistor capacitances,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 173–184, Mar. 1987.
    • (1987) IEEE Trans. Computer-Aided Design , vol.CAD-6 , pp. 173-184
    • Iwai, H.1    Pinto, M.R.2    Rafferty, C.R.3    Oristian, J.E.4    Dutton, R.W.5
  • 50
    • 0023345738 scopus 로고
    • Analysis of MOSFET capacitances and their behavior at short-channel lengths using an ac device simulator
    • Mar.
    • Y. Ohkura, T. Toyabe, and H. Masuda, “Analysis of MOSFET capacitances and their behavior at short-channel lengths using an ac device simulator,” IEEE Trans. Computer Aided Design, vol. CAD-6, pp. 423–430, Mar. 1987.
    • (1987) IEEE Trans. Computer Aided Design , vol.CAD-6 , pp. 423-430
    • Ohkura, Y.1    Toyabe, T.2    Masuda, H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.